| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2014: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Outline of Final Research Achievements |
In design process of microcomputers or FPGA devices, more efficient design verification is demanding. In simulation-based verification, the method for improving a quantitative metric called coverage is called coverage driven verification. In this research we uses machine learning for Bayesian networks for generating input patterns for simulation. Focusing on simulation parameters for the transition of signals in the design, our proposed method shows that coverage can be improved more quickly than the other existing methods.
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