Investigation of control technique and circuit topology for power supply on chip
| Project/Area Number |
25630111
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Power engineering/Power conversion/Electric machinery
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
ABE Seiya 九州工業大学, 大学院生命体工学研究科, 准教授 (40423488)
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| Project Period (FY) |
2013-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2013: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
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| Keywords | Power SoC / DC-DCコンバータ / 制御 / 高周波 / 集積化電源 / 制御技術 / 回路技術 / 電源 / デジタル制御 / POL / パワーSoC |
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| Outline of Final Research Achievements |
In recent years, a power supply on chip (SoC) has been attracted attentions of many researchers because itrealize ultimate miniaturization of a power supply. However it can handle small capacity per POL and is necessary to connect parallel at heavy loading conditions. In addition, high-frequency switching of more than 10MHz is required for shrinking the volume of the POL. In this study, we propose the novel concept of digitally controlled POLs suitable for power SoC. We also report the simulation and experimental results of the proposed concept. The results show that the proposed concepts enables to regulate output voltage and improves the efficiency over the wide range.
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Report
(3 results)
Research Products
(6 results)
