Basic research on ultra-low voltage MOS transistors aiming at sub-100mV operation
| Project/Area Number |
25630135
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Single-year Grants |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
SARAYA Takuya 東京大学, 生産技術研究所, 助手 (90334367)
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| Project Period (FY) |
2013-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2013: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
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| Keywords | 電子デバイス・集積回路 / 超低エネルギー / 半導体物性 / MOSトランジスタ / 大規模集積回路 / 超低消費電力 / サブスレッショルド / 電子デバイス・機器 / 低消費電力 |
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| Research Abstract |
The objective of this research is to develop a semiconductor device operating at as low as 100mV. In order to obtain high on/off ratio at low voltage, a MOS transistor with a floating gate is proposed, where threshold voltage (Vth) automatically decreases in the ON state while Vth increases in the OFF state. The device was actually fabricated, and the decrease in Vth in the ON state and the increase in Vth in the OFF stage was demonstrated at as low as 100mV. It was also demonstrated that the stability of an SRAM cell was improved at 100mV.
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Report
(2 results)
Research Products
(2 results)
