High-speed circuit development for the fast tracking trigger in high luminosity hadron collider
| Project/Area Number |
25800159
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Particle/Nuclear/Cosmic ray/Astro physics
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| Research Institution | Waseda University |
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Principal Investigator |
KIMURA Naoki 早稲田大学, 理工学術院, 助教 (30547617)
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| Project Period (FY) |
2013-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2013: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Keywords | LHC / ATLAS / トリガー / パターン認識 / FPGA / 飛跡検出 / LHC加速器 / ATLAS実験 / 高エネルギー / ハドロンコライダー / 高速飛跡検出 |
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| Outline of Final Research Achievements |
This study's purpose is establishment a new track recognition method by hardware system for the very high luminosity hadron collision experiment. Because very large quantity memory are necessary for real time tracking and to reduce the cost, it is desirable to develop the original ASIC tip which I specialized in a memory size, but I can largely reduce development time and cost by testing a circuit to implement with development in FPGA.
The track recognition method consisting of the application of ternary content addressable memory was implemented by FPGA and showed performance as I was expected. I was able to really implement track recognition in the same resolving power with around 30% of memory sizes. These results are applicable for track recognition or image recognition with the predicted evolution of the future FPGA-ASIC technology in real time to need future gathering speed, and a new study is in progress.
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Report
(3 results)
Research Products
(4 results)
