Complementary vertical tunnel FET aiming for low voltage and high speed operation by heterostructure design and miniaturization
| Project/Area Number |
26249046
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
鈴木 寿一 北陸先端科学技術大学院大学, 学内共同利用施設等, 教授 (80362028)
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| Co-Investigator(Renkei-kenkyūsha) |
KANAZAWA Toru 東京工業大学, 工学院, 助教 (40514922)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥41,470,000 (Direct Cost: ¥31,900,000、Indirect Cost: ¥9,570,000)
Fiscal Year 2016: ¥10,660,000 (Direct Cost: ¥8,200,000、Indirect Cost: ¥2,460,000)
Fiscal Year 2015: ¥11,700,000 (Direct Cost: ¥9,000,000、Indirect Cost: ¥2,700,000)
Fiscal Year 2014: ¥19,110,000 (Direct Cost: ¥14,700,000、Indirect Cost: ¥4,410,000)
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| Keywords | トンネルFET / ヘテロ接合 / 化合物半導体 / スタガード型ヘテロ構造 / 化合物半導体MOSFET / タイプIIヘテロ構造 / InGaAs MIS構造 / 分子線エピタキシー / 格子緩和成長 / 絶縁体-半導体界面 |
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| Outline of Final Research Achievements |
In order to improve the performance of the integrated circuit, it is necessary to simultaneously perform high on-current / low off-current / low power supply voltage. To realize that, research and development of a hetero structure and a fine multi gate structure combined with different materials for a tunnel FET (TFET) which operates on a different principle from the conventional one is necessary.
Based on the theoretical calculation, a double gate structure InGaAs / GaAsSb tunnel FET with a width of 20 nm was fabricated, and the subthreshold characteristic showing the change in current with respect to the gate voltage was confirmed to be 68 mV / dec, which is lower than the conventional one.
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Report
(4 results)
Research Products
(45 results)
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[Presentation] InGaAs channel for low supply voltage2015
Author(s)
Y. Miyamoto,T. Kanazawa, Y. Yonai, K. Ohsawa, Y. Mishima, M. Fujimatsu, K. Ohashi, S. Nestu, and S. Iwata
Organizer
47th Int. Conf. on Solid State Devices and Materials
Place of Presentation
Sapporo Convention Center
Year and Date
2015-09-28
Related Report
Int'l Joint Research / Invited
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