Nonvolatile power-gating technology based on CMOS/spintronics-hybrid CMOS circuits

• Project/Area Number: 26249049
• Research Category: Grant-in-Aid for Scientific Research (A)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Tokyo Institute of Technology
• Principal Investigator: Sugahara Satoshi 東京工業大学, 科学技術創成研究院, 准教授 (40282842)
• Project Period (FY): 2014-04-01 – 2019-03-31
• Project Status: Completed (Fiscal Year 2018)
• Budget Amount: ¥40,430,000 (Direct Cost: ¥31,100,000、Indirect Cost: ¥9,330,000); Fiscal Year 2018: ¥7,670,000 (Direct Cost: ¥5,900,000、Indirect Cost: ¥1,770,000); Fiscal Year 2017: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000); Fiscal Year 2016: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000); Fiscal Year 2015: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000); Fiscal Year 2014: ¥10,140,000 (Direct Cost: ¥7,800,000、Indirect Cost: ¥2,340,000)
• Keywords: CMOS / 待機時電力 / マイクロプロセッサ / SoC / SRAM / パワーゲーティング / ＳＲＡＭ / フリップフロップ / 集積回路 / メモリ / 低消費電力 / 低電圧 / 不揮発

Outline of Final Research Achievements

Nonvolatile power-gating (NVPG) that is an architecture employing nonvolatile state/data retention is expected to be a highly efficient energy reduction technique for high-performance CMOS logic systems. Nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) are required for the NVPG architecture. In this research project, design methodology for NV-SRAM using magnetic tunnel junctions (MTJs) and architectures for improving its energy efficiency are developed. A newly introduced hierarchical store-free (HSF) architecture is also highly effective at improving the energy efficiency. The energy performance is computationally analyzed and experimentally verified using circuit parameters extracted from fabricated test-element-group circuits of the NV-SRAM.

Academic Significance and Societal Importance of the Research Achievements

本研究課題では，CMOSロジックシステムにおいて極めて重要な問題となっている待機時電力を，不揮発記憶を活用したパワーゲーティング（NVPG）によって高効率に削減できる回路・アーキテクチャ技術を研究開発した．この目的には，従来の不揮発性メモリ技術ではその速度・エネルギー性能から応用は難しく適していない．そこで，SRAMやFFなど双安定記憶回路をNVPGに適合するように不揮発化した不揮発性双安定記憶回路（NV-SRAM，NV-FF）の開発を行った．本研究課題で開発したNVPG技術をMPやSoCに導入することで，従来のCMOS技術のみでは実現できない高効率の待機時電力削減が可能になる．

Research Products

• [Journal Article] Design and energy-efficient architectures for nonvolatile static random access memory using magnetic tunnel junctions (2019)
  • Author(s): Kitagata Daiki、Yamamoto Shuu’ichirou、Sugahara Satoshi
  • Journal Title: Japanese Journal of Applied Physics Volume: 58 Issue: SB Pages: SBBB12-SBBB12
  • DOI: 10.7567/1347-4065/ab00f5
  • NAID: 210000135442
  • Peer Reviewed
• [Journal Article] Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM (2017)
  • Author(s): Y. Takamura, Y. Shuto, S. Yamamoto, H. Funakubo, M. K. Kurosawa, S. Nakagawa, S. Sugahara
  • Journal Title: Solid-State Electronics Volume: 128 Pages: 194-199
  • Peer Reviewed / Acknowledgement Compliant
• [Presentation] Design and Performance of Virtually Nonvolatile Retention Flip-Flop Using Dual-Mode Inverters (2018)
  • Author(s): D. Kitagata, S. Yamamoto, and S. Sugahara
  • Organizer: IEEE 2nd New Generation of Circuits & Systems Conference
  • Int'l Joint Research
• [Presentation] Virtually Nonvolatile Retention SRAM cell Using Dual-Mode Inverters (2018)
  • Author(s): D. Kitagata, H. Yoshida, S. Yamamoto, and S. Sugahara
  • Organizer: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
  • Int'l Joint Research
• [Presentation] A New Architecture of Store Energy and Latency Reduction for Nonvolatile SRAM Based on Spintronics/CMOS-Hybrid Technology (2018)
  • Author(s): D. Kitagata, S. Yamamoto, and S. Sugahara
  • Organizer: 2018 International Conference on Solid State Device and Materials
  • Int'l Joint Research
• [Presentation] Virtually Nonovolatile Retention Flip-Flop Using FinFET Technology (2018)
  • Author(s): D. Kitagata, S. Yamamoto, and S. Sugahara
  • Organizer: 2018 IEEE Silicon Nanoelectronics Workshop
  • Int'l Joint Research
• [Presentation] Design and Circuit Performance of a New Piezoelectronic Transistor (2018)
  • Author(s): Y. Shiotsu, S. Yamamoto, Y. Shuto, H. Funakubo, M. K. Kurosawa, and S. Sugahara
  • Organizer: 2018 IEEE Silicon Nanoelectronics Workshop
  • Int'l Joint Research
• [Presentation] デュアルパワースイッチを用いた擬似不揮発性SRAMの設計と解析 (2018)
  • Author(s): 吉田隼，北形大樹，山本修一郎，菅原聡
  • Organizer: 第66回応用物理学会春季学術講演会
• [Presentation] 新構造ピエゾエレクトロニックトランジスタの低リーク設計とそのSRAMへの応用 (2018)
  • Author(s): 塩津勇作，山本修一郎，舟窪浩，黒澤実，菅原聡
  • Organizer: 第66回応用物理学会春季学術講演会
• [Presentation] 擬似不揮発性FFの速度性能優先設計とその回路性能 (2018)
  • Author(s): 北形大樹，松﨑翼，山本修一郎，菅原聡
  • Organizer: 第66回応用物理学会春季学術講演会
• [Presentation] デュアルモードインバータを用いた疑似不揮発性SRAMの設計と解析 (2018)
  • Author(s): 吉田隼，北形大樹，山本修一郎，菅原聡
  • Organizer: 第79回応用物理学会秋季学術講演会
• [Presentation] 新構造ピエゾエレクトロニックトランジスタの設計方法 (2018)
  • Author(s): 塩津勇作，山本修一郎，舟窪浩，黒澤実，菅原聡
  • Organizer: 第79回応用物理学会秋季学術講演会
• [Presentation] デュアルモードインバータを用いた疑似不揮発性FFの設計と解析 (2018)
  • Author(s): 北形大樹，山本修一郎，菅原聡
  • Organizer: 第79回応用物理学会秋季学術講演会
• [Presentation] 新構造ピエゾエレクトロニックトランジスタの設計とそのデバイス・回路性能 (2018)
  • Author(s): 塩津勇作，山本修一郎，周藤悠介，舟窪浩，黒澤実，菅原聡
  • Organizer: 第65回応用物理学会春季学術講演会
• [Presentation] 階層型ストアフリー電源遮断を用いた不揮発性SRAMのエネルギー性能 (2018)
  • Author(s): 北形大樹，山本修一郎，菅原聡
  • Organizer: 第65回応用物理学会春季学術講演会
• [Presentation] 不揮発性SRAMの設計とエネルギー性能の解析 (2017)
  • Author(s): 北形大樹，周藤悠介，山本修一郎，菅原聡
  • Organizer: 第64回応用物理学会春季学術講演会
  • Place of Presentation: 東京
  • Year and Date: 2017-03-19
• [Presentation] 不揮発性SRAMのアーキテクチャとエネルギー性能 (2017)
  • Author(s): 北形大樹，周藤悠介，山本修一郎，菅原聡
  • Organizer: 電気情報通信学会集積回路研究会
  • Invited
• [Presentation] Hierarchical Store-Free Architecture for Nonvolatile SRAM Using STT-MTJs (2017)
  • Author(s): D.Kitagata, S.Yamamoto, and S.Sugahara
  • Organizer: EEE International Electron Devices Meeting (IEDM) MRAM special session 2017
  • Int'l Joint Research
• [Presentation] Piezoelectronic Transistor for Low-Voltage High-Speed Integrated Electronics (2017)
  • Author(s): Sugahara, Y.Shuto, S.Yamamoto, H.Funakubo, and M.K.Kurosawa
  • Organizer: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference
  • Int'l Joint Research
• [Presentation] 強磁性トンネル接合を用いた不揮発性SRAMの待機時電力削減能力 (2017)
  • Author(s): 北形大樹，山本修一郎，菅原聡
  • Organizer: 第78回応用物理学会秋季学術講演会
• [Presentation] Energy Performance of Nonvolatile Power-Gating SRAM Using SOTB Technology (2016)
  • Author(s): Y. Shuto, S. Yamamoto, and S. Sugahara
  • Organizer: 46th European Solid-State Device/Circuit Conference (ESSDERC/ESSCIRC)
  • Place of Presentation: Lausanne, Switzerland
  • Year and Date: 2016-09-12
  • Int'l Joint Research
• [Presentation] Design and Implementation of Nonvolatile Power-Gating SRAM Using SOTB Technology (2016)
  • Author(s): Y. Shuto, S. Yamamoto, and S. Sugahara
  • Organizer: International Symposium on Low Power Electronics and Design (ISLPED)
  • Place of Presentation: San Francisco, USA
  • Year and Date: 2016-08-08
  • Int'l Joint Research
• [Presentation] Nonvolatile Power-gating Architecture for SRAM using SOTB Technology (2016)
  • Author(s): Y. Shuto, S. Yamamoto, and S. Sugahara
  • Organizer: 2016 IEEE Silicon Nanoelectronics Workshop (SNW 2016)
  • Place of Presentation: Honolulu, USA
  • Year and Date: 2016-06-12
  • Int'l Joint Research
• [Presentation] New power-gating architectures using nonvolatile retention: Comparative study of nonvolatile power-gating (NVPG) and normally-off architectures for SRAM (2016)
  • Author(s): Y. Shuto, S. Yamamoto, and S. Sugahara
  • Organizer: 29th IEEE International Conference on Microelectronic Test Structures (ICMTS)
  • Place of Presentation: Yokohama, Japan
  • Year and Date: 2016-03-28
  • Int'l Joint Research / Invited
• [Presentation] CMOS/スピントロニクス融合技術による待機時消費電力削減アーキテクチャ (2015)
  • Author(s): 周藤悠介, 山本修一郎, 菅原聡
  • Organizer: 応用物理学会スピントロニクス研究会
  • Place of Presentation: 千代田区, 東京
  • Year and Date: 2015-11-12
  • Invited
• [Presentation] Quantitative comparison of power-gating architectures for FinFET-based nonvolatile SRAM using spintronics retention technology (2015)
  • Author(s): Yusuke Shuto, Shuu’ichirou Yamamoto, Satoshi Sugahara
  • Organizer: 4th Berkeley Symposium on Energy Efficient Electronic Systems (E3S)
  • Place of Presentation: Berkeley, CA, USA
  • Year and Date: 2015-10-01
  • Int'l Joint Research
• [Presentation] 不揮発性SRAMを用いたパワーゲーティングアーキテクチャの定量比較 (2015)
  • Author(s): 周藤悠介, 山本修一郎, 菅原聡
  • Organizer: 第76回応用物理学会秋季学術講演会
  • Place of Presentation: 名古屋市, 愛知
  • Year and Date: 2015-09-13
• [Presentation] Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology (2015)
  • Author(s): Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
  • Organizer: 18th Design, Automation and Test in Europe (DATE15)
  • Place of Presentation: Grenoble, France
  • Year and Date: 2015-03-09 – 2015-03-13
• [Presentation] Comparative Study of Power-Gating Architectures for Nonvolatile SRAM Cells Based on spintronics Technology (2014)
  • Author(s): Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara
  • Organizer: 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2014)
  • Place of Presentation: Okinawa, Japan
  • Year and Date: 2014-11-17 – 2014-11-20
• [Presentation] Near-threshold voltage operation of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture (2014)
  • Author(s): 7.Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara
  • Organizer: 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S2014)
  • Place of Presentation: Millbrae, CA, USA
  • Year and Date: 2014-10-06 – 2014-10-10
• [Presentation] 0.5V operation and performance of nonvolatile SRAM cell based on pseudo-spin-FinFET architecture (2014)
  • Author(s): 8.Yusuke Shuto, Shuu'ichirou Yamamoto, and Satoshi Sugahara
  • Organizer: 2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2014)
  • Place of Presentation: Yokohama, Japan
  • Year and Date: 2014-09-09 – 2014-09-11
• [Presentation] Design and performance of nonvolatile SRAM cells based on pseudo-spin-FinFET architecture (2014)
  • Author(s): Y. Shuto, S. Yamamoto, and S. Sugahara
  • Organizer: 2014 IEEE Silicon Nanotechnology Workshop (SNW2014)
  • Place of Presentation: Honolulu, HI, USA
  • Year and Date: 2014-06-08 – 2014-06-09
• [Book] Spin-transistor technology for spintronics/CMOS hybrid logic circuits and systems (2016)
  • Author(s): S. Sugahara, Y. Shuto, and S. Yamamoto
  • Total Pages: 25
  • Publisher: John Wiley & Sons, Ltd
• [Patent(Industrial Property Rights)] 電子回路 (2017)
  • Inventor(s): 菅原聡,北形大樹,山本修一郎
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2017
• [Patent(Industrial Property Rights)] 電子回路 (2017)
  • Inventor(s): 菅原 聡,山本 修一郎
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2017
• [Patent(Industrial Property Rights)] 双安定回路と不揮発性素子とを備える記憶回路 (2017)
  • Inventor(s): 周藤 悠介,山本 修一郎,菅原 聡
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2017
  • Overseas
• [Patent(Industrial Property Rights)] 磁気抵抗素子および記憶回路 (2016)
  • Inventor(s): 菅原 聡,高村 陽太,中川 茂樹
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2016
  • Acquisition Date: 2018
  • Overseas
• [Patent(Industrial Property Rights)] ピエゾ抵抗体をチャネルに用いたトランジスタおよび電子回路 (2015)
  • Inventor(s): 周藤 悠介,黒澤 実,舟窪 浩,山本 修一郎,菅原 聡
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2015
  • Acquisition Date: 2019
  • Overseas
• [Patent(Industrial Property Rights)] ピエゾ抵抗体をチャネルに用いたトランジスタおよび電子回路 (2015)
  • Inventor(s): 周藤 悠介,黒澤 実,舟窪 浩,山本 修一郎,菅原 聡
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2015
  • Acquisition Date: 2018
  • Overseas
• [Patent(Industrial Property Rights)] 記憶回路 (2015)
  • Inventor(s): 菅原 聡,周藤 悠介,山本 修一郎
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2015
  • Acquisition Date: 2018
  • Overseas
• [Patent(Industrial Property Rights)] 記憶回路 (2015)
  • Inventor(s): 菅原 聡,周藤 悠介,山本 修一郎
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2015
  • Acquisition Date: 2017
  • Overseas
• [Patent(Industrial Property Rights)] 双安定回路と不揮発性素子とを備える記憶回路 (2015)
  • Inventor(s): 周藤 悠介,山本 修一郎,菅原 聡
  • Industrial Property Rights Holder: JST
  • Industrial Property Rights Type: 特許
  • Filing Date: 2015
  • Acquisition Date: 2017
  • Overseas