| Project/Area Number |
26330063
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Toyohashi University of Technology |
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Principal Investigator |
Ryotaro Kobayashi 豊橋技術科学大学, 工学(系)研究科(研究院), 准教授 (40324454)
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| Co-Investigator(Kenkyū-buntansha) |
嶋田 創 名古屋大学, 情報基盤センター, 准教授 (60377851)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2016: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2015: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | 低消費電力技術 / メニーコア / プロセッサ / クラスタ |
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| Outline of Final Research Achievements |
Recent CPU has many cores and cache memory on a chip to utilize thread level parallelism and decrease access speed gap between cores and main memory. It is preferable to use IO execution core and decrease the cache energy consumption for better area/energy efficiency. However, the increase in the way of IO supplies very slight improvement and it is not easy to decrease the supply voltage of the cache. Firstly, we focus the ALU cascading, which introduces the hardware complexity of the bypass circuits. To address this problem, we propose the mechanism with the small bypass circuits with the early rearrangement of independent instructions. Secondly, we focus dynamic voltage and frequency scaling (DVFS), which brings an idle time between the end of the cache access and the start of the next clock cycle. We utilize the idle time to dynamically change the cache configuration which decreases the energy without performance loss.
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