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Higher Reliable Task Assignment Method for Embedded Multiprocessor

Research Project

Project/Area Number 26330064
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionOsaka University

Principal Investigator

TAKEUCHI YOSHINORI  大阪大学, 情報科学研究科, 准教授 (70242245)

Co-Investigator(Kenkyū-buntansha) 今井 正治  大阪大学, 情報科学研究科, 教授 (50126926)
劉 載勲  大阪大学, 情報科学研究科, 助教 (70726976)
Project Period (FY) 2014-04-01 – 2017-03-31
Project Status Completed (Fiscal Year 2016)
Budget Amount *help
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Keywordsマルチプロセッサ・システム / 高信頼性 / スケジューリング / タスク割当
Outline of Final Research Achievements

This research studies reliability of future high performance system by multiprocessor systems. Such a system should be operated under low voltage in order to keep away from high thermal operation and aging degradation of systems. On the other hand, operations under low voltage suffers from voltage source fluctuation by system current. There may occur some errors by voltage drop. This research proposed a reliable mechanism which limits the current changes and does not suffer much performance loss under the constraint of current fluctuation.

Report

(4 results)
  • 2016 Annual Research Report   Final Research Report ( PDF )
  • 2015 Research-status Report
  • 2014 Research-status Report
  • Research Products

    (4 results)

All 2016 2015 Other

All Presentation (3 results) (of which Int'l Joint Research: 2 results,  Invited: 1 results) Remarks (1 results)

  • [Presentation] Proposal of an Efficient Clock-Gating Mechanism for Multi-Core Processors to reduce Power Supply Noise2016

    • Author(s)
      Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai
    • Organizer
      The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2016)
    • Place of Presentation
      Kyoto Research Park, Kyoto, Japan
    • Year and Date
      2016-10-24
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 源ノイズ削減のためのマルチコアプロセッサ向けクロックゲーティング機構の提案2016

    • Author(s)
      川部 純, 武内 良典, 劉 載勲, 今井 正治
    • Organizer
      DAシンポジウム2016
    • Place of Presentation
      山代温泉 ゆのくに天祥
    • Year and Date
      2016-09-14
    • Related Report
      2016 Annual Research Report
  • [Presentation] Higher reliable multiprocesosr system for embedded systems considering power source fluctuation2015

    • Author(s)
      Yoshinori Takeuchi
    • Organizer
      15th International Forum on MPSoC for Software-defined Hardware 2015 (MPSoC 2015)
    • Place of Presentation
      Ventura Beach Marriott (Ventura, CA, USA)
    • Year and Date
      2015-07-13
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research / Invited
  • [Remarks] 集積システム設計学講座ホームページ

    • URL

      http://www-ise1.ist.osaka-u.ac.jp/lab/

    • Related Report
      2016 Annual Research Report 2015 Research-status Report

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Published: 2014-04-04   Modified: 2018-03-22  

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