Studies on Non-Scan based Synthesis for Testability and Test Generation from High-Level Design for LSIs
| Project/Area Number |
26330071
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Nihon University |
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Principal Investigator |
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| Research Collaborator |
FUJIWARA Hideo
YOSHIMURA Masayoshi
MIYASE Kohei
YAMAZAKI Hiroshi
MATSUNAGA Yusuke
YOTSUYANAGI Hiroyuki
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2014: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | 動作合成 / テスト生成 / 低消費電力 / トロイ検出 / テスト容易化合成 / テスト環境生成 / マルチサイクルキャプチャテスト / 故障診断 / 高位合成 / テスト容易化バインディング / テスト容易化スケジューリング / テスト容易化機能的時間展開モデル / 低消費電力指向テスト圧縮 / テストポイント挿入 / コントローラ拡大 / 階層テスト生成 / テスト容易化機能的時間展開モデル生成 / 低消費電力指向テスト生成 / マルチサイクルキャプチャテスト生成 |
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| Outline of Final Research Achievements |
In this research, we target to perform manufacturing test for LSI (Large Scale Integrated Circuits) with high quality and low cost while guaranteeing the security of confidential information embedded on LSI. Thus, our purpose is to establish techniques to ensure the reliability and the safety for LSI.
We have proposed synthesis-for-testability and design-for-testability methods at high level of LSI design, a method of easily testable functional information extraction to generate efficient test generation models, test generation methods for low power and test compaction, and a hardware Trojan detection method for three years.
We contributed to the realization of safe LSI testing with high quality and low cost using low hardware overhead.
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Report
(4 results)
Research Products
(47 results)
