Research on the design of a fast updatable index generation circuit
| Project/Area Number |
26330072
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Meiji University |
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Principal Investigator |
Sasao Tsutomu 明治大学, 理工学部, 専任教授 (20112013)
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| Co-Investigator(Renkei-kenkyūsha) |
IGUCHI Yukihiro 明治大学, 理工学部, 専任教授 (60201307)
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| Research Collaborator |
Butler Jon T.
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| Project Period (FY) |
2014-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2016: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2014: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | 国際研究者交流、米国 / 線形関数 / 関数分解 / ルータ / CAM(連想メモリ） / パターンマッチング / 書き換え可能回路 / 国際研究者交流、米 / ５ CAM(連想メモリ） / インデックス生成関数 / CAM(連想メモリ) |
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| Outline of Final Research Achievements |
Content Addressable Memories (CAMs) are widely used in the routers for the internet, pattern matching, and cache memories in computers. By using CAMs, a high-speed pattern matching is possible. Unfortunately, CAMs are expensive and dissipate high power. The author invented an index generation unit (IGU) that uses general-purpose memories and small amount of hardware. It works as a CAM, but is much less expensive. In this research, the author developed a fast update method for an IGU.
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Report
(5 results)
Research Products
(61 results)
