• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Development of an Additional-data-wrapping Circuit for a Network Monitoring

Research Project

Project/Area Number 26420364
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Communication/Network engineering
Research InstitutionThe University of Shiga Prefecture

Principal Investigator

Kieiji Kisshine  滋賀県立大学, 工学部, 教授 (20512776)

Project Period (FY) 2014-04-01 – 2018-03-31
Project Status Completed (Fiscal Year 2017)
Budget Amount *help
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2016: ¥260,000 (Direct Cost: ¥200,000、Indirect Cost: ¥60,000)
Fiscal Year 2015: ¥520,000 (Direct Cost: ¥400,000、Indirect Cost: ¥120,000)
Fiscal Year 2014: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Keywords高速回路 / 周波数ラッピング / ネットワーク監視 / ルーティング / LSI / 回路 / 通信システム / 高効率 / 多重化 / ネットワーク / フレーム信号 / 伝送 / 変調 / ラベリング / 高速 / 線形性 / 高分解能
Outline of Final Research Achievements

Recently, a large amount of information is transmitted and received on optical communications systems. Researchers have been improving the capacity of optical communications systems in which deep sub-micron devices are used for the circuit elements in the optical transmission equipment. We propose the labeling transmission system which enable the system to transmit additional information with the original data frame. By using this system, the information for monitoring and managing network can be transmitted and received with data frame between network nodes. To confirm the advantages of the proposed system, we constructed a prototype system comprising a FPGA, discrete elements and the data-wrapping circuit consisting of high-speed deep sub-micron transistors were used. We investigated investigate the system performance. The measured characteristics show the advantage of the system and the feasibility of the an efficient and low-cost network without processors.

Report

(5 results)
  • 2017 Annual Research Report   Final Research Report ( PDF )
  • 2016 Research-status Report
  • 2015 Research-status Report
  • 2014 Research-status Report
  • Research Products

    (32 results)

All 2017 2016 2015 2014

All Journal Article (5 results) (of which Int'l Joint Research: 2 results,  Peer Reviewed: 5 results,  Open Access: 2 results,  Acknowledgement Compliant: 2 results) Presentation (27 results) (of which Int'l Joint Research: 10 results)

  • [Journal Article] Simple and Low Power Highly Sensitive Frequency Demodulator Circuit for 10-Gb/s Transmission System for Labeling Signal2017

    • Author(s)
      Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine
    • Journal Title

      IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

      Volume: 17 Issue: 6 Pages: 733-740

    • DOI

      10.5573/jsts.2017.17.6.733

    • Related Report
      2017 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Design of High-linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS2017

    • Author(s)
      Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine
    • Journal Title

      IEIE JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

      Volume: 17 Issue: 6 Pages: 742-749

    • DOI

      10.5573/jsts.2017.17.6.742

    • Related Report
      2017 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Simple Routing Control System for 10 Gb/s Data Transmission Using a Frequency Modulation Technique2016

    • Author(s)
      Daichi Omoto, Keiji Kishine*, Hiromi Inaba, and Tomoki Tanaka
    • Journal Title

      IEIE Transactions on Smart Processing and Computing

      Volume: vol. 5, no. 3 Issue: 3 Pages: 199-206

    • DOI

      10.5573/ieiespc.2016.5.3.199

    • Related Report
      2016 Research-status Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] A 32-Gb/s Inductorless Output Buffer Circuit with Adjustable Pre-emphasis in 65-nm CMOS2016

    • Author(s)
      Tomoki Tanaka, Keiji Kishine, Akira Tsuchiya, Hiromi Inaba, and Daichi Omoto
    • Journal Title

      IEIE Transactions on Smart Processing and Computing

      Volume: vol. 5, no. 3 Issue: 3 Pages: 207-214

    • DOI

      10.5573/ieiespc.2016.5.3.207

    • Related Report
      2016 Research-status Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS2015

    • Author(s)
      Keiji Kishine, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
    • Journal Title

      IEEE Transactions on Circuits and Systems. I

      Volume: vol. 62, no. 5 Issue: 5 Pages: 1288-1295

    • DOI

      10.1109/tcsi.2015.2416812

    • Related Report
      2015 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Presentation] FPGAを用いたFIRフィルタによる脈拍センサ信号の雑音除去2017

    • Author(s)
      荒内航貴,森本安紀,作田健,植村宙夢,香田夏幸,岸根桂路
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      名城大学 天白キャンパス(名古屋市)
    • Year and Date
      2017-03-22
    • Related Report
      2016 Research-status Report
  • [Presentation] ラべリング信号伝送システムにおける受信回路高速化の検討2017

    • Author(s)
      香田夏幸,古市康祐,植村宙夢,荒内航貴,野村幸平,岸根桂路
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      名城大学 天白キャンパス(名古屋市)
    • Year and Date
      2017-03-22
    • Related Report
      2016 Research-status Report
  • [Presentation] FPGAによるフレーム信号変調システムの検討2017

    • Author(s)
      野村幸平,植村宙夢,古市康祐,岸根桂路
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      名城大学 天白キャンパス(名古屋市)
    • Year and Date
      2017-03-22
    • Related Report
      2016 Research-status Report
  • [Presentation] 25-Gb/sCDRの低消費電力化を目指したD-FFの比較検討2017

    • Author(s)
      野口凌輔,岸根桂路,古市康祐,植村宙夢,桂井宏明・中野慎介・野坂秀之・野河正史
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      名城大学 天白キャンパス(名古屋市)
    • Year and Date
      2017-03-22
    • Related Report
      2016 Research-status Report
  • [Presentation] 25-Gb/s Clock and Data Recovery IC Using Latch Load Combined with CML Buffer Circuit for Delay Generation with 65-nm CMOS2017

    • Author(s)
      Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi,  Daichi Omoto, Hiromi Inaba, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka and Keiji Kishine
    • Organizer
      2017 IEEE International Symposium on Circuits and Systems
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS2017

    • Author(s)
      Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, and Makoto Nakamura: “Design Method for Inductorless Low-Noise Amplifiers with Active Shunt-Feedback in 65-nm CMOS
    • Organizer
      2017 IEEE International SoC Design Conference
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Compact Implementation IIR filter in FPGA for Noise Reduction of Sensor Signal2017

    • Author(s)
      Koki Arauchi, Shohei Maki,Toshiyuki Inoue, Akira Tsuchiya, and Keiji Kishine
    • Organizer
      2017 IEEE International SoC Design Conference
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGA-Based Transceiver Circuit for Labeling Signal Transmission System2017

    • Author(s)
      Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue
    • Organizer
      2017 IEEE International SoC Design Conference
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGAを用いた変調回路に関する検討2016

    • Author(s)
      野村幸平,植村宙夢,古市康祐,岸根桂路
    • Organizer
      電気関係学会関西連合大会
    • Place of Presentation
      大阪府 大阪府立大学 中百舌鳥キャンパス
    • Year and Date
      2016-11-22
    • Related Report
      2016 Research-status Report
  • [Presentation] FPGAを用いたFIRフィルタによる生体センサ信号の雑音除去の検討2016

    • Author(s)
      荒内航貴,森本安紀,作田建,岸根桂路
    • Organizer
      電気関係学会関西連合大会
    • Place of Presentation
      大阪府 大阪府立大学 中百舌鳥キャンパス
    • Year and Date
      2016-11-22
    • Related Report
      2016 Research-status Report
  • [Presentation] エンファシス回路によるハーフレート識別回路の広帯域化に関する検討2016

    • Author(s)
      寺本慎也,古市康祐,植村宙夢,岸根桂路
    • Organizer
      電気関係学会関西連合大会
    • Place of Presentation
      大阪府 大阪府立大学 中百舌鳥キャンパス
    • Year and Date
      2016-11-22
    • Related Report
      2016 Research-status Report
  • [Presentation] Cross Current Suppression Control for Parallel Operation System Contructed with Two Electric Power  Converters under Different Output2016

    • Author(s)
      Ryota Fujisawa, Hiromi Inaba, Keiji Kishine, Keisuke Ishikura, and Kazuki Ikebata
    • Organizer
      The 19th International Conference on Electrical Machines and Systems (ICEMS2016)
    • Place of Presentation
      Chiba, Japan
    • Year and Date
      2016-11-13
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] 36-Gb/s CDR IC using simple passive loop filter combined with a passive load in phase detector2016

    • Author(s)
      Kosuke Furuichi, Hiromu Uemura, Natsuyuki Koda, Hiromi Inaba, and Keiji Kishine
    • Organizer
      International SoC Design Conference (ISOCC2016)
    • Place of Presentation
      Jeju, South Korea
    • Year and Date
      2016-10-23
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] Design of High-Linearity Delay Detection Circuit for 10-Gb/s Communication System in 65-nm CMOS2016

    • Author(s)
      Natsuyuki Koda, Kosuke Furuichi, Hiromu Uemura, Hiromi Inaba, and Keiji Kishine
    • Organizer
      International SoC Design Conference (ISOCC2016)
    • Place of Presentation
      Jeju, South Korea
    • Year and Date
      2016-10-23
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system2016

    • Author(s)
      Tomoki Tanaka, Keiji Kishine, Akira Tsuchiya, Hiromi Inaba, and Daichi Omoto
    • Organizer
      International SoC Design Conference (ISOCC2016)
    • Place of Presentation
      Jeju, South Korea
    • Year and Date
      2016-10-23
    • Related Report
      2016 Research-status Report
    • Int'l Joint Research
  • [Presentation] ラベリング信号伝送システムにおける高周波変調回路の設計2016

    • Author(s)
      植村宙夢,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      九州 福岡
    • Year and Date
      2016-03-15
    • Related Report
      2015 Research-status Report
  • [Presentation] 群遅延特性を考慮した遅延検波回路の高性能化検討2016

    • Author(s)
      古市康祐,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      九州 福岡
    • Year and Date
      2016-03-15
    • Related Report
      2015 Research-status Report
  • [Presentation] ラベリング信号伝送システムにおける検波回路構成簡易化の検討2016

    • Author(s)
      香田夏幸,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      九州 福岡
    • Year and Date
      2016-03-15
    • Related Report
      2015 Research-status Report
  • [Presentation] A 32-Gb/s output buffer circuit with doubled pre-emphasis in 65-nm CMOS2016

    • Author(s)
      Tomoki Tanaka, Keiji Kishine, Daichi Omoto, Hiromi Inaba, and Akira Tsuchiya
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC2016)
    • Place of Presentation
      Danang, Vietnam
    • Year and Date
      2016-01-27
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research
  • [Presentation] Simple routing contorol system for 10-Gb/s data toransmission using a frequency modulation technique2016

    • Author(s)
      Daichi Omoto, Keiji Kishine, Hiromi Inaba, and Tomoki Tanaka
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC2016)
    • Place of Presentation
      Danang, Vietnam
    • Year and Date
      2016-01-27
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research
  • [Presentation] ラベリング信号伝送システムにおける送信回路に関する検討2015

    • Author(s)
      植村宙夢,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電気関係学会関西連合大会
    • Place of Presentation
      大阪
    • Year and Date
      2015-11-14
    • Related Report
      2015 Research-status Report
  • [Presentation] エンファシス回路による遅延検波回路の広帯域化2015

    • Author(s)
      古市康祐,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電子情報通信学会ソサイエティ大会
    • Place of Presentation
      宮城
    • Year and Date
      2015-09-09
    • Related Report
      2015 Research-status Report
  • [Presentation] ジッタ検出回路に関する検討2015

    • Author(s)
      沖中正季,岸根桂路,稲葉博美,尾本大地,田中友規
    • Organizer
      電気・電子・情報関係学会東海支部連合大会
    • Place of Presentation
      愛知
    • Year and Date
      2015-09-08
    • Related Report
      2015 Research-status Report
  • [Presentation] プリエンファシス機能付き25Gb/s動作出力バッファ回路の試作評価2015

    • Author(s)
      田中友規,岸根桂路,土谷亮(京大),尾本大地,稲葉博美
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      滋賀
    • Year and Date
      2015-03-10 – 2015-03-13
    • Related Report
      2014 Research-status Report
  • [Presentation] ラべリング信号検出回路におけるFM遅延検波回路の高分解能化検討2015

    • Author(s)
      尾本大地,稲葉博美,岸根桂路,田中友規
    • Organizer
      電子情報通信学会総合大会
    • Place of Presentation
      滋賀
    • Year and Date
      2015-03-10 – 2015-03-13
    • Related Report
      2014 Research-status Report
  • [Presentation] 25-Gb/s inductorless output buffer circuit with a pre-emphasis in 65-nm CMOS2014

    • Author(s)
      Tomoki Tanaka, Keiji Kishine, Hiromi Inaba, and Akira Tsuchiya
    • Organizer
      International SoC Design Conference (ISOCC2014)
    • Place of Presentation
      Jeju, Korea
    • Year and Date
      2014-11-03 – 2014-11-06
    • Related Report
      2014 Research-status Report
  • [Presentation] A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops2014

    • Author(s)
      Keiji Kishine, Hiroshi Inoue, Hiromi Inaba,Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
    • Organizer
      The 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
    • Place of Presentation
      Melbourne, Australia
    • Year and Date
      2014-06-01 – 2014-06-05
    • Related Report
      2014 Research-status Report

URL: 

Published: 2014-04-04   Modified: 2019-03-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi