Development of an Additional-data-wrapping Circuit for a Network Monitoring
| Project/Area Number |
26420364
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Communication/Network engineering
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| Research Institution | The University of Shiga Prefecture |
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Principal Investigator |
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| Project Period (FY) |
2014-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2016: ¥260,000 (Direct Cost: ¥200,000、Indirect Cost: ¥60,000)
Fiscal Year 2015: ¥520,000 (Direct Cost: ¥400,000、Indirect Cost: ¥120,000)
Fiscal Year 2014: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
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| Keywords | 高速回路 / 周波数ラッピング / ネットワーク監視 / ルーティング / LSI / 回路 / 通信システム / 高効率 / 多重化 / ネットワーク / フレーム信号 / 伝送 / 変調 / ラベリング / 高速 / 線形性 / 高分解能 |
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| Outline of Final Research Achievements |
Recently, a large amount of information is transmitted and received on optical communications systems. Researchers have been improving the capacity of optical communications systems in which deep sub-micron devices are used for the circuit elements in the optical transmission equipment. We propose the labeling transmission system which enable the system to transmit additional information with the original data frame. By using this system, the information for monitoring and managing network can be transmitted and received with data frame between network nodes. To confirm the advantages of the proposed system, we constructed a prototype system comprising a FPGA, discrete elements and the data-wrapping circuit consisting of high-speed deep sub-micron transistors were used. We investigated investigate the system performance. The measured characteristics show the advantage of the system and the feasibility of the an efficient and low-cost network without processors.
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Report
(5 results)
Research Products
(32 results)
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[Presentation] 25-Gb/s Clock and Data Recovery IC Using Latch Load Combined with CML Buffer Circuit for Delay Generation with 65-nm CMOS2017
Author(s)
Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka and Keiji Kishine
Organizer
2017 IEEE International Symposium on Circuits and Systems
Related Report
Int'l Joint Research
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