A 3D Processor Architecture Co-Designed with Dependable Processing
| Project/Area Number |
26540018
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
Kobayashi Hiroaki 東北大学, サイバーサイエンスセンター, 教授 (40205480)
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| Co-Investigator(Renkei-kenkyūsha) |
TAKIZAWA HIROYUKI 東北大学, 大学院情報科学研究科, 准教授 (70323996)
EGAWA RYUSUKE 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
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| Project Period (FY) |
2014-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2015: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | 3次元メモリ / チェックポイントリスタート機構 / プロセッサアーキテクチャ / 3次元積層メモリ / ディペンダビリティ / チェックポインティング |
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| Outline of Final Research Achievements |
The objective of this study is to establish a novel processor architecture that realize both high performance and high dependability in the execution of a wide variety of applications by using 3D die-stacking technology toward the post-Moore’s era. In particular, we have developed a 3D die-stacking memory subsystem architecture integrated with processor cores and its data management mechanism for highly power-efficient and high-throughput memory hierarchy. In addition, we have also developed on-line checkpoint/restart mechanism by using a 3D die-stacking on-chip memory to increase dependability of the processor. The proposed architecture has been evaluated quantitatively by using a wide variety of applications and its effectiveness and limitation have been clarified and discussed.
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Report
(3 results)
Research Products
(10 results)
