A Study on on-chip memories suitable for near-threshold voltage operation

• Project/Area Number: 26540021
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Computer system
• Research Institution: Kyoto University
• Principal Investigator: Ishihara Tohru 京都大学, 情報学研究科, 准教授 (30323471)
• Project Period (FY): 2014-04-01 – 2017-03-31
• Project Status: Completed (Fiscal Year 2016)
• Budget Amount: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000); Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2014: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
• Keywords: 電子デバイス・機器 / 低消費電力・高エネルギー密度 / エネルギー効率化

Outline of Final Research Achievements

We have developed on-chip memory subsystems running with very low supply voltages. It has a functionality to stably run with very low supply voltages down to 0.25V. We have designed memory circuits integrating our idea for saving the area and energy consumption, which demonstrated that the energy efficiency of our memory circuit is twice better than existing on-chip SRAMs. We also integrated the memory circuits on microprocessor chips. The processor chip well runs with less than 0.3V voltage supply. We have obtained several awards such as IPSJ Yamashita Memorial Award and IEEE SSCS Japan Chapter VDEC Design Award which are given for the achievements in this research project.

Research Products

• [Presentation] A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory (2016)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: The 20th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: 京都リサーチパーク、京都府京都市
  • Year and Date: 2016-10-24
  • Int'l Joint Research
• [Presentation] Fully Digital On-Chip Memory Using Minimum Height Standard Cells for Near-Threshold Voltage Computing (2016)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: International Workshop on Power and Timing Modeling, Optimization and Simulation
  • Place of Presentation: Bremen, Germany
  • Year and Date: 2016-09-21
  • Int'l Joint Research / Invited
• [Presentation] 広範囲な動作性能領域においてエネルギー最小点追跡を可能にするオンチップメモリ (2016)
  • Author(s): 塩見準、石原亨、小野寺秀俊
  • Organizer: 情報処理学会DAシンポジウム
  • Place of Presentation: 山代温泉ゆのくに天祥、石川県加賀市
  • Year and Date: 2016-09-14
• [Presentation] Variability- and Correlation-Aware Logical Effort for Near-Threshold Circuit Design (2016)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: International Symposium on Quality Electronic Design
  • Place of Presentation: Santa Clara Convention Center, Santa Clara, California, USA
  • Year and Date: 2016-03-15
  • Int'l Joint Research
• [Presentation] A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region (2016)
  • Author(s): Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: Asia and South Pacific Design Automation Conference
  • Place of Presentation: Holiday Inn, Sands Cotai, Macau
  • Year and Date: 2016-01-26
  • Int'l Joint Research
• [Presentation] サブスレッショルド領域におけるラッチ回路の動作安定性モデル (2015)
  • Author(s): 鎌苅竜也，塩見準，石原亨，小野寺秀俊
  • Organizer: 情報処理学会DAシンポジウム
  • Place of Presentation: 山代温泉ゆのくに天祥、石川県加賀市
  • Year and Date: 2015-08-26
• [Presentation] 統計的タイミングモデルに基づくニアスレッショルド回路のゲートサイジング (2015)
  • Author(s): 塩見準，石原亨，小野寺秀俊
  • Organizer: 情報処理学会DAシンポジウム
  • Place of Presentation: 山代温泉ゆのくに天祥、石川県加賀市
  • Year and Date: 2015-08-26
• [Presentation] A Variability-Aware Energy-Efficient On-Chip Memory for Near-Threshold Operation using Cell-Based Structure (2015)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: The 19th Workshop on Synthesis And System Integration of Mixed Information technologies
  • Place of Presentation: Evergreen Resort Hotel, Yilan, Taiwan
  • Year and Date: 2015-03-16 – 2015-03-17
• [Presentation] An Energy-Efficient On-Chip Memory Structure for Variability-Aware Near-Threshold Operation (2015)
  • Author(s): Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera
  • Organizer: 16th International Symposium on Quality Electronic Design
  • Place of Presentation: San Jose, California, USA
  • Year and Date: 2015-03-03 – 2015-03-05
• [Presentation] ニアスレッショルド電圧動作に適した単一電源で動作する高歩留まりオン チップメモリの設計 (2014)
  • Author(s): 塩見準，石原亨，小野寺秀俊
  • Organizer: 情報処理学会DAシンポジウム2014
  • Place of Presentation: ホテル下呂温泉水明館、岐阜県下呂市
  • Year and Date: 2014-08-28 – 2014-08-29
• [Patent(Industrial Property Rights)] 半導体装置及び半導体装置の製造方法 (2016)
  • Inventor(s): 石原亨、塩見準
  • Industrial Property Rights Holder: 石原亨、塩見準
  • Industrial Property Rights Type: 特許
  • Filing Date: 2016-01-20