| Project/Area Number |
26630148
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
SARAYA Takuya 東京大学, 生産技術研究所, 助手 (90334367)
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| Project Period (FY) |
2014-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
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| Keywords | 特性ばらつき / MOSFET / シリコンナノワイヤトランジスタ / 離散不純物ゆらぎ / 単一不純物 / VLSI / 半導体物性 / MOSトランジスタ / 大規模集積回路 / ナノワイヤトランジスタ / 統計分布 |
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| Outline of Final Research Achievements |
The objective of this research is to clarify the statistic nature of nanoscale silicon nanowire transistors with intrinsic channel. Silicon nanowire transistors with width ranging from 2nm to 7nm were fabricated and their characteristics were measured. It is found that threshold voltage of 7nm-wide nanowire transistors shows normal distribution, while threshold voltage of 2nm-wide nanowire transistors deviates from the normal distribution, possibly due to the effect of single impurity atom and quantum effects by nanowire width fluctuations.
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