| Project/Area Number |
26820125
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
Iizuka Tetsuya 東京大学, 大規模集積システム設計教育研究センター, 准教授 (10552177)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2015: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2014: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Keywords | 電子デバイス・機器 / 集積回路 / 時間-デジタル変換 / 時間領域信号 / パルス縮小型 / 時間－デジタル変換 / 飛行時間型計測機器 / パルス幅 / 時間ーデジタル変換 / 時間差積分 |
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| Outline of Final Research Achievements |
In nano-scale CMOS processes, a time resolution is becoming superior to a voltage resolution due to the high-speed transistors and the reduced supply voltage. This research, especially for time-of-flight measurement applications, first proposes a fine-resolution and wide-range time-to-digital converter (TDC). The proposed TDC realizes a fine time resolution based on a novel pulse-shrinking scheme that utilizes a built-in offset pulse and a completion detection schemes. This TDC is used as the fine stage of the hierarchical TDC that realizes 2ps resolution and 80ns input range at the same time. As one of the basic time-mode signal processing elements, a novel time-mode accumulator, which inherently avoids the mismatch by using only one ring to hold the time-mode signal, is also proposed and demonstrated. In addition, a power supply noise detection and reduction circuit based on an on-chip TDC is proposed and demonstrated.
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