| Project/Area Number |
26870574
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Nanostructural physics
Electron device/Electronic equipment
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| Research Institution | Keio University |
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Principal Investigator |
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| Research Collaborator |
UCHIDA Ken 慶應義塾大学, 理工学部, 教授 (30446900)
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2016: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2015: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2014: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Keywords | ナノ電子デバイス / 自己加熱効果 / アナログ特性 / フォノン輸送 / ナノワイヤ / SOI MOSFET / FinFET / フォノン / バリスティック輸送 / 自己加熱 / トランジスタ温度分布 / 界面熱抵抗 / ナノ半導体 / 熱伝導率 |
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| Outline of Final Research Achievements |
In this research, the temperature distributions of operated nanoscale electron devices and the impacts of its temperature increase on device performances were investigated. From electrical and thermal device simulations, a low-power device design strategy for nanoscale 3D transistors was proposed by optimizing thermal characteristics. Furthermore, from experimental evaluations of thermal conductivity of silicon nanowires, it was clarified that conventional thermal evaluation methods might contain some errors in estimations of operation tempeartures in nanoscale semiconductor electron devices.
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