Computational model for VLSI systems
| Project/Area Number |
60550252
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| Research Category |
Grant-in-Aid for General Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Research Field |
計算機工学
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| Research Institution | TOHOKU UNIVERSITY |
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Principal Investigator |
MARUOKA Akira Faculty of Engineering, Tohoku University, Sendai, 工学部・情報工学科, 教授 (50005427)
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| Project Period (FY) |
1985 – 1987
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| Project Status |
Completed (Fiscal Year 1987)
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| Budget Amount *help |
¥1,300,000 (Direct Cost: ¥1,300,000)
Fiscal Year 1987: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1986: ¥400,000 (Direct Cost: ¥400,000)
Fiscal Year 1985: ¥500,000 (Direct Cost: ¥500,000)
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| Keywords | VLSI Complexity, / Partitioning / Expander / Communication Time / Computation Time / Verification for Correctness / Learning Algorithm / 擬似ランダム / 超LSI / 平列計算 / 通信コスト / 正当性の検証 / 回路分割 |
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| Research Abstract |
Technological evolution of VLSI makes VLSI circuits very important as components in large scale computing systems. In this report we explore a model of computation for VLSI, which reflects computational potential of VLSI, characterize performance of VLSI, and develop design technique to implement efficient algorithms. The results obtained in the project are as follows. In Chapter 1, we model the computational problem to be solved as a directed acyclic graph, with nodes corresponding to computed values, and arcs denoting dependencies. In this chapter we obtain a nontrivial trade-off between the communication time and computation time required to compute a collection of values whose dependencies form a grid. Using the graph model for computational problems, we can reduce the problem of designing efficient algorithms to the one of constructing graphs with some property. In literature it is shown that the optimal sorting algorithm is obtained by using bipartite graphs, called expanders, wi
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th some property on the connectivity. Chapter 2 gives a way of constructing the expanders explicitly. In Chapter 3 it is proved that, for any finite set of one-dimensional linear mappings, the bipartite graphs whose connectivity is defined by the linear mappings are not expanders. In Chapter 4, hardware algorithms based on cellular automata are surveryed. Chapte 5 discusses on the notion of amplification of logical functions and gives upper and lower bounds on the size of Boolean formula to realize certain amplification. Furthermore, it is shown that, using the Boolean formula which realize certain amplification efficiently, we can construct threshold functions with small size. As the size of VLSI chips increases, they are broken down into subcircuits to keep the total complexity inthe scope of each individual designer manageable. Chapter 6 deals with the problem of estimating the minimum number of the subcircuits of a Boolean circuits, to compute a given Boolean function, partitioned in a manner that interconnections between subcircuits are limited. Chapter 7 discusses about a hardware verification system based upon <lamdda>-notation. Chapter 8 deals with learning algorithms for Boolean functions. Finally, Chapter 9 studies a method for efficiently constructing a pseudo-random invertible permita-tion generator from a pseudo-random function generator. Less
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Report
(2 results)
Research Products
(12 results)
