1999 Fiscal Year Final Research Report Summary
Study for a radiation-hardened CMOS circuitdirectly fabricated on a detector-grade silicon wafer with an application of a rapid nitridation process
| Project/Area Number |
09354003
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 展開研究 |
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| Research Field |
素粒子・核・宇宙線
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| Research Institution | High Energy Accelerator Research Organization |
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Principal Investigator |
IKEDA Hirokazu Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization, Associate Professor, 素粒子原子核研究所, 助教授 (10132680)
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| Co-Investigator(Kenkyū-buntansha) |
FUKUNAGA Chikara Tokyo Metropolitan University, College of Arts and Science, Associate Professor, 教養部, 助教授 (00189961)
TAJIMA Hiroyasu University of Tokyo, Department of Physics, Research Associate, 理学部, 助手 (80222107)
MATSUDA Takeshi Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization, Associate Professor, 素粒子原子核研究所, 助教授 (10029564)
OKUNO Shoji Kanagawa University, Faculty of Engineering, Research Associate, 工学部, 助手 (90281451)
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| Project Period (FY) |
1997 – 1999
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| Keywords | High Energy Physics / Particle Tracking Detector / Silicon Detector / CMOS Preamplifier / CMOS Integrated Circuit / Rapid Thermal Nitridation / Radiation Damage / Radiation-hardening |
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| Research Abstract |
In order to apply for a high luminosity electron-positron collider experiment we have investigated a possibility of integrating strip and/or pixelde-tectors with a readout circuits. Since the circuits are irradiated by ionizing particles and gamma rays, the characteristics of transistors are easy to be degraded. In order to overcome the nature of a radiation damage, one way proposed was to apply a rapid thermal nitridation process for a gate oxide of a CMOS FET. We actually obtained an indication of an improvement in terms of a threshold shift and/or degradation in noise, there still remained a room for a further adjustment of process conditions. An alternative way was proposed to apply for a 0.8-micron CMOS process in place of the so-far employed 1.2-micron CMOS process, which revealed a significant improvement in terms of a noise degradation coefficient for an increment of a radiation dose as well as an initial noise slope.
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