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1999 Fiscal Year Final Research Report Summary

Massively Parallel Networks in 3D-Stacked Silicon Wafers

Research Project

Project/Area Number 09480051
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionJapan Advanced Institute of Science and Technology

Principal Investigator

HORIGUCHI Susumu  Japan Advanced Institute of Science and Technology, Information Science, Professor, 情報科学研究科, 教授 (60143012)

Co-Investigator(Kenkyū-buntansha) INOGUCHI Yasushi  Japan Advanced Institute of Science and Technology, Information Center, Research Associate, 情報科学研究科, 助手 (90293406)
HAYASHI Ryouko  Japan Advanced Institute of Science and Technology, Information Science, Research Associate, 情報科学研究科, 助手 (30303332)
YAMAMORI Kunihito  Japan Advanced Institute of Science and Technology, Information Science, Research Associate, 情報科学研究科, 助手 (50293395)
TAKEDA Hirokatu  Yamagata University, Research Associate, 工学部, 助手 (90236472)
Project Period (FY) 1997 – 1999
KeywordsVLSI, ULSI / VLSI Reconfiguration / Massively Computer / 3D-Stacked Wafers / Hierarchical Network / Routing
Research Abstract

With the continuing advances in VLSI technology, multiprocessor systems with tens to hundreds of processing elements are expected to rival today's supercomputers in the next decade. Systems consisting of a few tens to a million processing elements have indeed been described in the literature. The development of such large scale systems will make numerous applications such as multi-media, computer vision, and modeling of physical phenomena to be feasible on desk-top workstations. However, a major issue in designing large scale multiprocessor systems is the construction of a flexible interconnection network to provide efficient inter-processor communication.
This research develops a hierarchically structured interconnection network, 'Tori connected mESHes' (TESH), which allows exploitation of computational locality as well as modular future expansion. Also, the network has reduced wiring and only a few ports per processor, features that are essential in cost-effective implementation of large scale computing systems. Further, it has a regular structure which makes addressing of nodes and message routing rather straightforward. The network also appears to permit 3-D stacked implementation. In part, this is due to the far fewer number of vertical wires needed than almost all known multi-computer networks. As is well known, parallelizing a problem is usually application-specific and system architecture dependent. Therefore, several applications such as sorting, merging, FFT, and convolution, have been mapped to the network as paradigms in.

  • Research Products

    (18 results)

All Other

All Publications (18 results)

  • [Publications] V.K. Jain, T. Ghirmai and S. Horiguchi: "TESH : A New Hierarchical Interconnection Network for Massively Parallel Computing"IEICE Trans. Information and Systems. Vol. E80-D, No. 9. 837-846 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y. Inoguchi, T. Matsuzawa and S. Horiguchi: "SRT Interconnection Network on 3D Stacked Implementation by Considering Thermo-Radiation"Proc. IEEE International Conference on Innovative Systems in Silicon. Austin, U.S.A.. 41-51 (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.K. Jain, and S. Horiguchi: "VLSI Considerations for TESH : A New Hierarchical Interconnection Network for 3-D Integration"IEICE Trans. VLSI Systems. Vol. 6, No. 3. 346-353 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.K. Jain, and S. Horiguchi: "Architecture, Defect Tolerance and Buffer Design for a New ATM Switch"IEICE Trans. on Components, Packaging, and Manufacturing Tech. -Part B. Vol. 21, No. 4. 338-345 (1998)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] H. Liu, D.F. Hsu and S. Horiguchi: "Generalized Shuffle-Exchange Digraphs : Hamiltonian Properties"Proc. of 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, U.S.A.. (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Y. Touyama and S. Horiguchi: "Performance Evaluation of Practical Parallel Computation Model LogPQ"Proc. IEEE Int'l Symp. on Parallel Architectures, Algorithms and Networks Fremantle, Australia. (ISPAN '99). 216-221 (1999)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Susumu Horiguchi edited: "IEICE Trans. on Information and Systems, Vol. E80-D"Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing. (1997)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V. K. Jain, T. Ghirmai and S. Horiguchi: "TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing"IEICE Trans. Information and Systems. Vol. E80-D, No. 9. 837-846 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Susumu Horiguchi edited: "Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing"IEICE Trans. on Information and Systems. Vol. E80-D. (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Horiguchi and M. Konuki: "The Horizontal Rotate Crossed Cube : HCQ Interconnection Network"Proc. of IEEE International Symposium on Parallel Architectures, Taipei, Taiwan. 118-124 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] S. Horiguchi, T. Ooki and V. K. Jain: "Network Performance of TESH: A New Hierarchical Interconnection Network"Proc. International Symposium on Dynamic Modeling of Information Systems, Yamagata, Japan. 49-60 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Inoguchi, T. Matsuzawa and S. Horiguchi: "SRT Interconnection Network on 3D stacked Implementation by Considering Thermo-Radiation"Proc. of IEEE International Conference on Innovative Systems in Silicon, Austin, U.S.A.. 41-51 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. N. Shen, X.T. Chen, S. Horiguchi and F. Lombardi: "On the Multiple Fault Diagnosis of Multistage Interconnection Network: The Lower Bound and the CMOS Fault Model"Proc. of the 26-th International Conference on Parallel Processing IEEE CS Press, Bloomingdale, U.S.A.. 350-353 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Inoguchi and S. Horiguchi: "Shifted Recursive Tours Interconnection for High Performance Computing"Proc. of IEEE High Performance Computing in Asia, Seoul, Korea. 61-66 (1997)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. K. Jain and S. Horiguchi: "VLSI Considerations for TESH: A New Hierarchical Interconnection Network for 3-D Integration"IEEE Trans. VLSI Systems. Vol. 6, No. 3. 346-353 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. K. Jain and S. Horiguchi: "Architecture, Defect Tolerance and Buffer Design for a New ATM Switch"IEEE Trans. on Components, Packaging, and Manufacturing Tech.-Part B. Vol. 21, No. 4. 338-345 (1998)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H. Liu, D. F. Hsu and S. Horiguchi: "Generalized Shuffle-Exchange Digraphs: Hamiltonian Properties"Proc. of 1999 IEEE International Symposium on Circuits and Systems, Orlando, Florida, U.S.A.. (1999)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y. Touyama and S. Horiguchi: "Performance Evaluation of Practical Parallel Computation Model LogPQ"Proc. IEEE Int'l Symp. on Parallel Architectures, Algorithms and Networks (ISPAN'99), Fremantle, Australia. 216-221 (1999)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2001-10-23  

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