| Co-Investigator(Kenkyū-buntansha) |
ZHENG Ruotong VLSI Design and Education Center, The University of Tokyo, Research Associate, 大規模集積システム設計教育研究センター, 助手 (50292959)
IKEDA Makoto VLSI Design and Education Center, The University of Tokyo, Lecturer, 大規模集積システム設計教育研究センター, 講師 (00282682)
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| Research Abstract |
In this research, pseudo asynchronous design, which can achieve an average-case performance without much hardware overhead compared with conventional synchronous system, is studied. Furthermore, datapath based on the pseudo asynchronous concept is designed.
In pseudo asynchronous datapath, data flow in pipeline is controlled by a completion signal. However, due to the generation delay of completion detection in previous design, the overall speed was limited. n our research, to generate the completion signal as fast as the alculation speed, completion prediction method is proposed. As a case tudy, the completion prediction method is applied to both ripple carry adder (RCA) and carry lookahead adder (CLA). Circuit simulation results show that speed improvement is 20% to 66% in average case compared with corresponding conventional synchronous adders. Such a kind of adder is designed to be implemented as LSI IP (Intellectual Property) without much effort.
We have been performing research work on low power LSI design by means of data encoding on inter/intra-chip bus interface. However, when we apply this method to a synchronous system, the data transfer delay problem due to the encoding has to be solved. In asynchronous or pseudo asynchronous system, which is constructed with blocks that don't have constant delay, the delay time generated in bus interface is not critical.
In this year, we concentrate our research focus on data encoding without redundant bit, which allows least changes on bus interface except for the driver circuits. With statistical calculations on data transfer, encoding codebook is updated in real time. As a result, although redundant bit is not used, up to 20% signal transitions in bus are cut off.
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