| Co-Investigator(Kenkyū-buntansha) |
TANG Zhen Toyama University, Faculty of Engineering, Professor (Until 1999), 工学部, 教授 (90227299)
TANNO Koichi Miyazaki University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (50260740)
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| Research Abstract |
In this research, we have developed a high-performed multi-valued static RAM (SRAM) composed of a qauntizer with floating-gate MOS transistors (vMOS). In 1998, we designed down literal circuits using two vMOS's as the fundamental circuits. The quaternary qauntizer was implemented with the down literal circuit and two binary CMOS AND/OR gates. The quaternary SRAM was realized with this qauntizer added control circuits of writing, memorizing and reset. In 1999, we engrossed the layout design of the quaternary qauntizer and required the fabrication of the LSI chip to VDEC.The smallest size of the cell can be realized. The simulation results with HSpice showed the confirmation of the normal operation and the lower speed. Then, we tried to design some vMOS's with various size of input capacitors. In 2000, we examined the fabricated chips. The results of the experiment presented the confirmation of the theoretical operation and the lower speed as same as the simulation results. The problem of the low speed is occurred by the existance of initial charges in the floating gates in a vMOS.Therefore, we can not complete the LSI chip of the multi-valued SRAM.We will try to continue this work, and design the layout of the multi-valued SRAM.On the other hand, down literal circuits using vMOS's has been developed. The performances grows highly, and they are applied to many circuits, such as multi-input variable-threshold circuits, pass gates, multi-level generators, multi-valued MIN circuits and multi-valued complemented circuits. These circuits can used as improvement of a qauntizer and they are necessary to compose a multi-valued SRAM.
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