| Co-Investigator(Kenkyū-buntansha) |
SAWADA Sunao Kyushu University, Grad.School of ISEE, Research Associate, 大学院・システム情報科学研究院, 助手 (70235464)
IWAIHARA Mizuho Kyushu University, Grad.School of ISEE, Associate Professor, 大学院・システム情報科学研究院, 助教授 (40253538)
YASUURA Hiroto Kyushu University, Grad.School of ISEE, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
ISHIHARA Tohru Univ.of Tokyo, VDEC, Research Associate, 大規模集積システム設計教育研究センター, 助手 (30323471)
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| Research Abstract |
The objective of this research project is to develop design methodologies for scalable system-LSI architectures. The project has performed the following research results.
(1) Development of scalable system-LSI emulator : The project has developed an emulator, which consists of a CPCI-based PC card and two FPGA-mounted CPCI cards, for enabling designers to explore large design space of system-LSI quickly.
(2) Development of architectures for scalable system-LSI and the design space : The project has developed a couple of technologies good for scalable system-LSI, such as (i) PPRAM (Parallel Processing RAM) architectures (inter-LSI communication interface, dynamically variable line-size cache, and so on), (ii) optimizing techniques for variable datapath/memorypath width, (iii) techniques for alleviating data/control dependences on CMP (chip multiprocessor), (iv) intra-LSI signaling technique reducing the effect of crosstalk.
(3) Development of CAD tools : The project has developed a couple
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of CAD tools, such as (i) realtime online profiler for detecting program hot-spots, (ii) hardware/software codesign environment for soft-core processor and Valen-C programs.
(4) Development and evaluation of high-performance/low-power microprocessor architectures : The project has developed a couple of technologies good for high-performance/low-power microprocessors, such as (i) dynamic module selection technique utilizing multiple functional modules with different performance/power properties, (ii) realtime task scheduling algorithm for DVS (dynamic voltage scaling) processors, (iii) power-aware memory hierarchy, (iv) cache memory architectures adapting CCC (common case computation) principle to memory reference behavior.
(5) Development of applications of scalable system-LSI : The project has developed some scalable system-LSI applications, including (i) RSA cipher processor, (ii) MPEG2 AAC decoder, (iii) special-purpose processor for ERI (electron repulsion integral) calculations in computational chemistry programs. Less
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