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2001 Fiscal Year Final Research Report Summary

Development of a Energy-Recovering Low-Power Processor Architecture.

Research Project

Project/Area Number 11558035
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 計算機科学
Research InstitutionFukuoka University

Principal Investigator

MOSHNYAGA Vasily  Faculty of Engineering, Assistant Prof., 工学部, 教授 (40243050)

Co-Investigator(Kenkyū-buntansha) ONODERA Hidetoshi  Kyoto Univ., Graduate Sch. Of Informatics. Professor, 工学研究科, 教授 (80160927)
TSURUTA Naoyuki  Faculty of Engineering, Assistant Prof., 工学部, 助教授 (60227478)
SUETSUGU Tadashi  Faculty of Engineering, Assistant Prof., 工学部, 助教授 (60279255)
Project Period (FY) 1999 – 2001
KeywordsProcessor / Architecture / Design Techniques / Low-Power / Date Reuse / Caches / Adiabatic Circuits / Energy Recovery
Research Abstract

(a) Development of a Energy-Recovering Processor Architecture and its prototype chip implementation. We investigated a new concept of Energy-Recovering Processor Architecture and presented techniques for its implementation. Due to adiabatic charge-recovering and instruction and, data reuse, the architecture lowers the energy consumption by almost two orders of magnitude in comparison to the traditional processor design. To evaluate the architecture, a prototype LSI chip have been designed and fabricated.
(b) Development of Architectural Techniques for Reducing Transition Activity of Processing Hardware.Several new schemes to minimize switching activity of functional units, and register files by datadriven operand encoding, adaptive bit-width compression, operand transformation, bypassing, etc. have been proposed. Unlike conventional techniques, these methods can dynamically disable the hardware bits whose values remain unchanged, thus reducing unnecessary signal variations as much as ha]f without affecting the processing accuracy. The schemes are simple and easy in implementation.
(c) Development of Architectural Techniques for Variable Voltage Reduction of System Memory. New circuit techniques for adaptive voltage reduction in instruction issue queue, data and instruction caches have been proposed. In contrast to existing design approaches, the methods dynamically adjust the supply voltage to the level of instruction parallelism (issue queue) as well as the locality of accesses (caches), reducing the energy dissipation in these units by a factor of two without any impact on performance and very small area overhead.

  • Research Products

    (31 results)

All Other

All Publications (31 results)

  • [Publications] V.G.Moshnyaga: "Issue Queue Energy Reduction Through Dynamic Voltage Scaling"IEICE Transactions on Electronics. E85-C(2). 272-278 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue, V.G.Moshnyaga, K.Murakami: "Trends in High-Performance, Low-Power Cache Memory"IEICE Transactions on Electronics. E85-C (2). 304-314 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue, V.G.Moshnyaga, K.Murakami: "Omitting Cache Look-Up for High-Performance, Low-Power"IEICE Transactions on Electronics. E85-C(2). 279-287 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga, H.Tsuji: "Reducing Cache Energy Dissipation through Dual-Voltage Supply"IEICE Transactions on Fundamentals in Electronics, Communications and Computer Science. E84-A(11). 2762-2768 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Reducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits"Journal of VLSI Signal Processing Systems. (accepted for publication). (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Inoue, V.G.Moshnyaga, K.Murakami: "Dynamic Tag-Check Omission : A Low Power Instruction Cache Architecture Exploiting Execution Footprints"Workshop on Power-Aware Computer Systems, (in Int.Symposium on High-Performance Computer Architecture). 15-22 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Energy Reduction in Queues and Stacks by Adaptive Bit-width Compression"ACM/IEEE International Symposium on Low-Power Electronic Design (ISLPED'2001). 22-27 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Cache Energy Reduction by Dual Voltage Supply"IEEE International Symposium on Circuits and Systems(ISCAS-2001). Vol.4. 922-925 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply"Workshop on Complexity-Effective Design (International. Symposium on Computer Architecture). 23-30 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Techniques for low energy processor architecture design"5th World Multi-conference on Systemics, Cybernetics and Informatics (SCI-2001). 45-52 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] J.Tanaka, H.Shin-ei, V.G.Moshnyaga: "An Experimental Comparison of Adiabatic Logic Styles"IEEE International Conference on Circuits and Systems (SCS'2001). 161-164 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Reducing switching activity of subtraction via bit truncation"IEEE International Conference on Circuits and Systems(SCS'2001). 165-168 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga, K.Inoue, Y.Yamamoto: "Reducing Activity of Multiplier-Accumulator Through Dynamic Operand Transformation"International Technical Conference on Circuits, Systems, Computers and Communications (ITCCSCC-2001). 143-146 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Reducing cache energy through dual voltage supply"Asia-South Pacific Design Automation Conference (ASP-DAC'2001). 302-305 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 井上弘士, モシニャガワシリー, 村上和彰: "実行頻度の偏りを利用した命令ROMの低消費エネルギー化手法"第15回 回路とシステム(軽井沢)ワークショップ. (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V.G.Moshnyaga: "Reducing Power Consumption of Video Memory Through Adaptive Bit-Width Compression"第14回 回路とシステム(軽井沢)ワークショップ. 549-554 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 辻 寛司, モシニャガ ワシリー: "2電源電圧によるキャッシュメモリの消費電力の最適化手法"第13回 回路とシステム(軽井沢)ワークショップ. 15-22 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] V. Moshinyaga: "lssue Queue Energy Reduction Through Dynamic l lEICE Trans. on Fundamentals Voltage Scaling"IEICE Trans. On Fundamentals in Electronics. @E85-C, +2. 272-278 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Inoue, V. Moshnyaga, K. Murakami: "Omitting Cache~Look-Up I IEICE Trans. on Fundamentals for High-Performaiice, Low-Power"IEICE Trans. On Fundamentals in Electronics. @E85-C, +2. 279-287 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Inoue, V. Moshnyaga, K. Murakami,: "Trends in High- Performance. Low-Power Cache Memory"IEICE Trans. On Fundamentals in Electronics. @E85-C, +2. 304-314 (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga, H. Tsuji,: "Reducing Cache Energy Dissipation IEICE Trans. on Fundamen- through Dual-Voltage Supply"IEICE Trans. On Fundamentals in Electronics. @E84-A, +11. 2762-2768 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga: "lleducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits"accepted for publication in Journal of VLSI Signal Processing. (2002)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga,: "Energy Reduction in Queues and Stacks by Adaptive Bit-width Compression"Proceedings of ACM/IEEE Int. Symp. On Low-Power Electronic Dsign. 22-27 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga,: "Reducmg Cache Energy through Dual Voltage Supply"Proceedings of Asia South Pacific Design Automation Conf.. 302-305 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga,: "Techniques for Low Energy Processor Architecture Design"Proceedings of 5th World MultiConf. On Systemics, Cybernetics and Informatics. 48-55 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] J. Tanaka, H. Shin-ei, V. Moshnyaga: "An Experimental Comparison of Adiabatic Logic Styles"Proceedings of the IEEE Int. Conf. on Circuits and Systems. 161-164 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga: "Reducing switching activity of subtraction via bit truncation"Proceedings of the IEEE Int. Conf. on Circuits and Systems. 165-168 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga: "keducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply"Proceedings of Workshop on Complexity-Effective Design. (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga, K. Inoue, and Y. Yamamoto: "Reducing Activity of Multiplier-Accumulator through Dynamic Operand Transformation"Proceedings of the Int. Tech. Conf. on Circuits, Systems, Computers and Communications. 143-146 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] V. Moshnyaga: "Cache Energy Reduction by Dual Voltage Supply"Proceedings of the IEEE Int. Symp. On Circuits and Systems.. @4. 922-925 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K. Inoue, V. Moshnyaga, K. Murakami,: "Dynamic Tag-Check Omission : A Low Power Instruction Cache Architecture Exploiting Execution Footprints"Proc. Of Workshop on PowerAware Computer System, Int. Symp. On High-Performance Computeer Architecture. 15-22 (2002)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2003-09-17   Modified: 2021-04-07  

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