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2001 Fiscal Year Final Research Report Summary

A Study on Automatic Layout Design System for Deep-Submicron High-Performance VLSI

Research Project

Project/Area Number 12555097
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section展開研究
Research Field 電子デバイス・機器工学
Research InstitutionHIROSHIMA UNIVERSITY (2001)
The University of Tokyo (2000)

Principal Investigator

KOIDE Tetsushi  Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor, ナノデバイス・システム研究センター, 助教授 (30243596)

Co-Investigator(Kenkyū-buntansha) KITAGAWA Akio  Kanazawa University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (10214785)
WAKABAYASHI Shin'ichi  Hiroshima University, Graduate School of Engineering, Associate Professor, 大学院・工学研究科, 助教授 (50210860)
Project Period (FY) 2000 – 2001
KeywordsDeep-submicron / VLSI / ULSI CAD / Layout design / Floorplanning / Placement and routing / Genetic algorithm / Performance-driven / Buffer block planning
Research Abstract

In this research, we studied new layout design methods for layout design automation of deep-submicron VLSI chips so as to solve the problems considering the performance of circuits, hard/soft macros, and minimizing of design time.
(1) Performance-driven circuit partitioning method
An circuit partitioning algorithm under path delay constraints was proposed to optimize performance of circuit.
(2) Performance-driven floorplanning methods
For floorplanning design with hard/soft macros, we proposed a performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion and showed effectiveness of the method.
(3) Performance-driven placement method
A timing-driven standard cell placement method based on cell-clustering and the new placement model, that is, ameba model was proposed.
(4) Performance-driven routing methods
For multi-routing layer model, we proposed a timing-driven hierarchical global routing method using a Steiner tree generation algorithm with wire sizing and buffer insertion.
(5) Performance-driven hierarchical buffer-block planning method
We proposed a hierarchical buffer block planning method, which divides the chip area into global bins, taking timing constraint into account.
(6) Applications of an adaptive genetic algorithm to performance-driven layout design
We newly proposed an adaptive genetic algorithm based on elite degree and applied to the layout design problems. We also implemented the proposed GA as GA accelerator LSI chips to speed up the execution and got a prospect of high-speed execution of number 10 times for performance-driven layout methods.

  • Research Products

    (48 results)

All Other

All Publications (48 results)

  • [Publications] Shingo Nakaya: "An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair"Proc. of 2000 IEEE International Symposium on Circuits and Systems. Vol.3. 65-68 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Jun'ichiro Minami: "An iterative improvement circuit partitioning algorithm under path delay constraints"IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. Vol.E83-A, No.12. 2569-2576 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Takahiro Deguchi: "Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer"Proc. 2000 Asia-South Pacific Design Automation Conference. 99-104 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shin'ichi Wakabayashi: "Genetic algorithm accelerator GAA-II"Proc. 2000 Asia-South Pacific Design Automation Conference. 9-10 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating a set of rectilinear Steiner trees in VLSI interconnect layout"Proc. International Conference on Chip Design Automation 2000. 243-248 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 若林 真一: "交差手法の適応的選択機能を組み込んだ遺伝的アルゴリズムのLSIチップによる実現"情報処理学会論文誌. Vol.41, No.6. 1766-1776 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大佐古 昌和: "ビルディングブロックレイアウトに対するバッファブロックプランニングの一手法"情報処理学会第63回(平成13年後期)全国大会講演論文集. 1. 1-25-1-26 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大佐古 昌和: "ULSIフロアプラン設計におけるバッファブロックプランニング手法"第3回IEEE広島支部学生シンポジウム論文集. 214-217 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Naoyoshi Toshine: "A parallel genetic algorithm with adaptive adjustment of genetic parameters"Proc. 2001 Genetic and Evolutionary Computation Conference. 679-686 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shinya Koizumi: "A RISC processor for high-speed execution of genetic algorithms"Proc. 2001 Genetic and Evolutionary Computation Conference. 1338-1345 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating a Steiner tree with wire sizing and buffer insertion"Proc. 2001 Genetic and Evolutionary Computation Conference. 1431-1438 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shingo Nakaya: "A performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion"Proc. Synthesis and System Integration of Mixed Technologies 2001. 226-233 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating a Steiner tree with wire sizing and buffer insertion"情報処理学会DAシンポジウム2000. 49-54 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 中矢 真吾: "バッファ挿入を考慮した概略配線とフロアプランを同時に求めるフロアプランニング手法"電子情報通信学会コンピュータシステム研究会技術研究報告. CPSY2000-64. 29-34 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 中矢 真吾: "概略配線を考慮したフロアプランニングに対するメタヒューリスティック手法"情報処理学会DAシンポジウム2001. 169-174 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 小泉 慎哉: "遺伝的アルゴリズムの高速実行に適した命令セットを持つRISCプロセッサDLX-GA"情報処理学会計算機アーキテクチャ研究会研究報告. ARC141-12. 65-70 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大佐古 昌和: "ULSIフロアプランニングにおける階層的バッファブロックプランニング手法"電子情報通信学会コンピュータシステム研究会技術研究報告. CPSY2001-64・101. 19-24 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 岩内 宣之: "クラスリングと新しい配置モデルに基づくタイミングドリブンスタンダードセル配置手法"電子情報通信学会コンピュータシステム研究会技術研究報告. CPSY2001-64・101. 25-30 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 中矢 真吾: "概略配線,バッファ挿入,タイミング制約を考慮したフロアプラニング手法"情報処理学会第61回(平成12年後期)全国大会講演論文集. 1. 1-107-1-108 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大佐古 昌和: "バッファ挿入と配線幅調整を考慮した概略配線手法の改良と実験的評価"平成12年度電気・情報関連学会中国支部 第51回連合大会講演論文集. 381-382 (2000)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 大佐古 昌和: "配線幅調整とバッファ挿入を考慮した概略配線に対する遺伝的アルゴリズム"2001年IEEE広島支部学生シンポジウム論文集. 202-207 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 山崎 晋哉: "メタヒューリスティックに基づくタイミング制約を考慮したフロアプランニング手法"情報処理学会第63回(平成13年後期)全国大会講演論文集. 1. 1-23-1-24 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 岩内 宣之: "クラスタリングと新しい配置モデルに基づくタイミングドリブンスタンダードセル配置手法"第3回IEEE広島支部学生シンポジウム論文集. 210-213 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 中矢 真吾: "適応的遺伝的アルゴリズムに基づくVLSIフロアプランニングの一手法"情報処理学会論文誌. Vol.43,No.5(印刷中). (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shingo Nakaya: "An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair"Proc. of 2000 IEEE International Symposium on Circuits and Systems. Vol.3. 65-68 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Jun'ichiro Minami: "An iterative improvement circuit partitioning algorithm under path delay constraints"IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol.E83-A, No.12. 2569-2576 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Takahiro Deguchi: "Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer"Proc. 2000 Asia-South Pacific Design Automation Conference. 99-104 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin' ichi Wakabayashi: "Genetic algorithm accelerator GAA-II"Proc. 2000 Asia-South Pacific Design1 Automation Conference. 9-10 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating a set of rectilinear Steiner trees in VLSI interconnect layout"Proc. International Conference on Chip Design Automation 2000. 243-248 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin'ichi Wakabayashi: "A VLSI floorplannning method based an adaptive genetic algorithm"IPSJ Journal. Vol.41, No.6. 1766-1776 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masakazu Ohsako: "A method of buffer block planning for building-block layout"Proc. of IPSJ the 63^<rd> General Conference. Vol.1. 1-25-1-26 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masakazu Ohsako: "A method of buffer block planning for ULSI floorplan design"Proc. of the 3^<rd> IEEE Hiroshima Student Symposium. 214-217 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Naoyoshi Toshine: "A parallel genetic algorithm with adaptive adjustment of genetic parameters"Proc. 2001 Genetic and Evolutionary Computation Conference. 679-686 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shinya Koizumi: "A RISC processor for high-speed execution of genetic algorithms"Proc. 2001 Genetic and Evolutionary Computation Conference. 1338-1345 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating Steiner tree with wire sizing and buffer insertion"Proc. 2001 Genetic and Evolutionary Computation Conference. 1431-1438 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shingo Nakaya: "A performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion"Proc. Synthesis and System Integration of Mixed Technologies 2001. 226-233 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shin'ichi Wakabayashi: "A genetic algorithm for generating a Steiner tree with wire sizing and buffer insertion"IPSJ Design Automation Symposium 2000. 49-54 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shingo Nakaya: "A floorplanning method for simultaneously determining module placement and global routers considering buffer insertion"IEICE Technical Report of Computer Systems. Vol.CPSY2000-64. 29-34 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shingo Nakaya: "A simultaneous global routing and floorplanning method based on meta-heuristics"IPSJ Design Automation Symposium 2001. 169-174 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shinya Koizumi: "A RISC processor DLX-GA with instruction set suitable for high-speed execution of a genetic algorithm"IPSJ SIG Notes of Computer Architecture. Vol.ARC141-12. 65-70 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masakazu Ohsako: "A hierarchical buffer block planning method for ULSI floorplanning"IEICE Technical Report of Computer Systems. Vol.CPSY2001-64-101. 19-24 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Nobuyuki Iwauchi: "A timing-driven standard-ceoll placement method based on cell-clustering and the new placement method"IEICE Technical Report of Computer Systems. Vol.CPSY2001-64-101. 25-30 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shingo Nakaya: "A floorplanning method with global routing considering buffer insertion under timing constraints"Proc. of IPSJ the 61^<st> General Conference. Vol.1. 1-107-1-108 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masakazu Ohsako: "Improvement and experimental evaluation of a global routing method with buffer insertion and wire sizing"Proc. of Electric and Information Associated Society, Tyugoku Chapter the 51^<st> Joint Conference. 381-382 (2000)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Masakazu Ohsako: "A genetic algorithm for global routing with considering wire sizing and buffer insertion"Proc. of the 3^<rd> IEEE Hiroshima Student Symposium. 202-207 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shinya Yamasaki: "A timing-driven floorplanning method based on meta-heuristics"Proc. of IPSJ the 63^<rd> General Conference. Vol.1. 1-23-1-24 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Nobuyuki Iwauchi: "A timing-driven standerd cell placement method based on cell-clustering and the new placement model"Proc. of the 3^<rd> IEEE Hiroshima Student Symposium. 210-213 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shingo Nakaya: "A VLSI floorplanning method based on an adaptive genetic algorithm"IPSJ Journal. Vol.43, No.5 (in press). (2002)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2003-09-17  

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