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2003 Fiscal Year Final Research Report Summary

Self-Timed High-Performance Real-time Processing Architecture

Research Project

Project/Area Number 13023210
Research Category

Grant-in-Aid for Scientific Research on Priority Areas

Allocation TypeSingle-year Grants
Review Section Science and Engineering
Research InstitutionKochi University of Technology

Principal Investigator

TERADA Hiroaki  Kochi University of Technology, Faculty of Engineering, Professor, 工学部, 教授 (80028985)

Project Period (FY) 2000 – 2002
KeywordsSelf-Timed Circuits / Data-Driven / Real-time / Mixed Integrated System / Multi-processor / Super-pipeline / IP address look-up / IP packet Classification
Research Abstract

The objective of this research project is to establish a high-performance network processor architecture based on the fully self-timed pipeline scheme. The following research results are obtained during the project. Next-generation high-speed network processors are required to achieve high-speed packet forwarding, to introduce new protocols and highly functional network services, and also to save electric power along with effective processing rate. The self-timed superpipelined data-driven architecture is one of the most promising architectures to satisfy these requirements because it is able to realize highly-functional and complex tasks by ultra-parallel processing software executable on flexible pipelined hardware.
(a)High-speed packet classification scheme Packet classification is one of heavy tasks in high-speed internet routers. We proposed a super-pipelined packet classification scheme. By using this scheme, we can classify about 12 M packets/second even in large scale internet exchange nodes having over 100 k classification rules.
(b)Priority based queueing scheme applicable to Diffserv The self-timed pipeline scheme is capable to realize high functionalities on silicon by virtue of its localized control. We proposed a priority-based queueing scheme as a highly-functional application of the self-timed pipeline scheme. A 0.18 um CMOS prototype chip of the proposed scheme using a folded self-timed pipeline structure was capable to queue and schedule 100 M packets/second autonomously.

  • Research Products

    (10 results)

All Other

All Publications (10 results)

  • [Publications] Daichi Morikawa: "Superpipelined IP-Address Lookups in a Data-Driven Network Processor"International Conference on Parallel and Distributed Computing and Systems. 431-438 (2001)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Shuji Sannomiya: "A Macroscopic Behavior Model for Self-Timed Pipeline Systems"International Workshop on Parallel and Distributed Simulation. 133-140 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Makoto Iwata: "100Mpackets/sec Fully Self-Timed Priority Queue : FQ"International Solid State Circuits Conference. 8.1 (2004)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Hideki, Hayashi: "***** Distributed Flow Control Scheme in Heterogeneous Network"Trans.On Information Processing Society. 45(2). 426-437 (2004)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Daichi Morikawa: "Super-Pipelined Implementation of IP Packet Classification"Journal of Intelligent Automation and Soft Computing. 9(掲載予定). (2004)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] Daichi, Morikawa: "Superpipelined IP-Address Lookups in a Data-Driven Network Processor"International Conference on Parallel and Distributed Computing and Systems. 431-438 (2001)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Shuji, Sannomiya: "A Macroscopic Behavior Model for Self-Timed Pipeline Systems"International Workshop on Parallel and Distributed Simulation. 133-140 (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Makoto, Iwata: "100Mpackets/sec Fully Self-Timed Priority Queue : FQ"International Solid State Sircuits Coference. 8.1. (2004)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Hideki, Hayashi: "Autonomous Distributed Flow Control Scheme in Heterogeneous Network"Trans. On Information Processing Society Japan. Vol.45, No.2. 426-437 (2004)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Daichi, Morikawa: "Super-Pipelined Implementation of IP Packet Classification"Journal of Intelligent Automation and Soft Computing (to be published). Vol.9. (2004)

    • Description
      「研究成果報告書概要(欧文)」より

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Published: 2005-04-19  

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