• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

2003 Fiscal Year Final Research Report Summary

Sequential image processor without decoding MPEG bitstream

Research Project

Project/Area Number 13680425
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionMusashi Institute of Technology

Principal Investigator

MIYAUCHI Arata  Musashi Institute of Technology, The department of computer science and media engineering, Professor, 工学部, 教授 (80166115)

Co-Investigator(Kenkyū-buntansha) ARAI Shuichi  Musashi Institute of Technology, The department of computer media engineering, Assistant Professor, 工学部, 助教授 (20212590)
Project Period (FY) 2001 – 2003
KeywordsMPEG / Architecture / Real time OS / Application program / Scheduling / Chip area estimation / Delay time estimation
Research Abstract

The objective of this research is to develop a MPEG bitstream processor without decoding the bitstream. Instead of designing the architecture of processor by designer, we investigate the system which analyses the application program and constructs processor architecture.
MPEG motion processing needs complicated programming and high performance environment to analyze parameters and to compute them in real time. We have proposed MBEP(Mpeg BitstrEam Processor) for MPEG movie processing. MI3EP has a dedicated architecture for computations of the MPEG movie. Inside MBEP, there are three main parts divided by their role. First part is the control part to control MBEP units by MBEP assembler code. Second part is the parameter detection part to extract parameters from bitstream. Third part is the arithmetic part to compute extracted parameters. We have developed the parameter detection part and the control part involved. Parameter formats of MPEG consist of n(1・n・32) bits. Taking out these parameters causes complex programming and a number of processes. Thekey points for the parameter detection are to find header information and to extract given numbers of bits. We improve the header information detection unit and the given n bits extraction unit.
According to extracting several parameters from movie data coded by MPEG2 MP@ML, MBEP shorten the processing time of parameter extraction and its time is less than real-time processing period. MBEP makes us achieve the desired objective of simple assembler program and speeding up movie processing.

  • Research Products

    (12 results)

All Other

All Publications (12 results)

  • [Publications] 相原 靖弘, 宮内 新, 荒井 秀一, 高田 広章: "機能分散型マルチプロセッサシステム向けITRONカーネルの開発"FIT2003. B-051. 251-252 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 河合 一慶, 宮内 新, 荒井 秀一: "アプリケーションプログラムを基にしたプロセッサアーキテクチャの自動生成 -タイミング制約からの面積見積り手法-"FIT2003. C-019. 335-336 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 栗崎 正和, 宮内 新, 荒井 秀一: "複数レジスタセットを用いたタスク切り替えの高速化"FIT2003. C-023. 343-344 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 原 淳, 宮内 新, 荒井 秀一: "ソフトウェア支援を用いたパイプラインプロセッサのフォワーディング機構の削減"FIT2003. C-011. 319-320 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 藤原 亮人, 宮内 新, 荒井 秀一: "データフローグラフ単位での広域命令スケジューリング"FIT2003. C-010. 317-318 (2003)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] 長谷川 光, 荒井 秀一, 宮内 新: "ターゲットの変更が可能な命令スケジューラに関する研究"FIT2002. C-12. 211-212 (2002)

    • Description
      「研究成果報告書概要(和文)」より
  • [Publications] K.Aida, A.Miyauchi, S.Arai: "A study on Image Processor without Decoding MPEG Bitstream"5T-4, IEICE2004. (2004)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] M.Kurisaki, A.Miyauhci, S.Arai: "A Speedup Technology of Task Switching using Plural Register Sets"1S-1, IEICE2004. (2004)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] Y.Aihara, A.Miyauchi, S.Arai, H.Takada: "Development of the ITRON kernel for functional distributed multiprocessor systems"B-051, F1T2003. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] K.Kawai, A.Miyauchi, S.Arai: "Automatic Generation of Processor Architecture Based on Application Program -The Estimation Method of Circuit area and Delay time -"C-019, FIT 2003. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] A.Fujiwara, A.Miyauchi, A.Arai: "Wide Area Instruction Scheduling on a Data Flow Graph"C-010, FIT2003. (2003)

    • Description
      「研究成果報告書概要(欧文)」より
  • [Publications] H.Hasegawa, S.Arai, A.Miyauchi: "Research on the instructions scheduler, which can change a target"C-12, FIT2002. (2002)

    • Description
      「研究成果報告書概要(欧文)」より

URL: 

Published: 2005-04-19  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi