High-performance and Low-Power Memory Management for the Era of Many-Channel Memories

2017 Fiscal Year Final Research Report

• Project/Area Number: 16H06613
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Single-year Grants
• Research Field: Computer system
• Research Institution: Tohoku University
• Principal Investigator: Sato Masayuki 東北大学, 情報科学研究科, 助教 (50781308)
• Research Collaborator: Kobayashi Hiroaki ; Egawa Ryusuke ; Toyoshima Takuya
• Project Period (FY): 2016-08-26 – 2018-03-31
• Keywords: メモリシステム

Outline of Final Research Achievements

This project proposes the high-performance and low-power management mechanism for many-channel memories, which is realized by the address-mapping schemes that limit the number of accessed channels, and the memory controller that can switch the address-mapping schemes.
The proposed address-mapping schemes change where the channel address is taken from bits of the physical address. These schemes successfully limit the number of channels accessed by executing applications, and the performance/power trade-off can be selected by switching these schemes.
The proposed memory controller can dynamically switch the address-mapping schemes. It also realizes the migration of the application data to maintain the consistency of the data placement when switching the address-mapping schemes. The evaluation results show that the memory controller can be realized by the reasonable costs of hardware and data migration.

Free Research Field

計算機アーキテクチャ