Circuit Wiring Design Method for Preventing the Oscillatory False Triggering of GaN Power Devices

2018 Fiscal Year Final Research Report

• Project/Area Number: 16K06223
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Power engineering/Power conversion/Electric machinery
• Research Institution: Okayama University
• Principal Investigator: Hiraki Eiji 岡山大学, 自然科学研究科, 教授 (20284268)
• Co-Investigator(Kenkyū-buntansha): 梅谷 和弘 岡山大学, 自然科学研究科, 助教 (60749323)
• Project Period (FY): 2016-04-01 – 2019-03-31
• Keywords: GaNデバイス / 連鎖的誤動作 / コモンソースインダクタンス

Outline of Final Research Achievements

Ultra-high-speed, low on-resistance GaN-FETs are attracting attention as next-generation power semiconductor devices, and are becoming essential for the development of small-sized, high-efficiency power supplies. However, since high speed operation is possible, there is a concern about increase in noise. Since the GaN-FET has a low on-off threshold voltage, it is prone to malfunction. Since this malfunction may destroy the GaN-FET itself, it is a major obstacle to the industrial application of the GaN-FET.
In this research, we focused on the chain-like malfunction peculiar to GaN-FET, clarified the relationship between the malfunction mechanism and the circuit parasitic inductance, and developed the circuit wiring design method that can make full use of the high-speed switching characteristics possessed by GaN.

Free Research Field

パワーエレクトロニクス

Academic Significance and Societal Importance of the Research Achievements

次世代パワー半導体素子として超高速かつ低オン抵抗のGaN-FETが注目されているが，誤動作が産業応用に対する大きな障害となっている。本研究は，GaNデバイスの連鎖的誤動作の発生原理を解明し，適切な回路設計によって誤動作を抑制することが可能であることを示した。このことは，GaNデバイスの普及に向けた大きな前進である。