A study on low delay network topology for a large scale parallel computing system

2019 Fiscal Year Final Research Report

• Project/Area Number: 17K00082
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Kumamoto University
• Principal Investigator: IIDA Masahiro 熊本大学, 大学院先端科学研究部(工), 教授 (70363512)
• Project Period (FY): 2017-04-01 – 2020-03-31
• Keywords: グラフ処理 / 概略計算 / FPGA / リコンフィギャラブルシステム

Outline of Final Research Achievements

In this work, we developed an algorithm to connect the research results of the Degree/Diameter Program to the Order/Degree Program. It is shown that the ODP can be solved by manually applying the Cayley graph to the ODP, and the results are reported in the IEICE journal. In addition, the graph processing accelerator proposed a data structure for processing graphs in streams, which was presented at the IEICE Technical Committee on Reconfigurable Systems (RECONF). In the development of the graph processing accelerator, it became clear that the calculation of the mean shortest path length ASPL was a problem, but it was not solved. However, with this consideration, a serial approximate adder was invented and a patent was applied.

Free Research Field

コンピュータシステム

Academic Significance and Societal Importance of the Research Achievements

グラフ処理に対する新しいアプローチとして，本研究課題で実施した内容は学術的な意義が高い．また，研究過程で生まれたシリアル概略加算器は，グラフ処理のみならず様々な処理に適用できる可能性があることから，学術的，社会的意義は計り知れない．