Development of Power Consumption Model of Low-voltage and Low-power Sub-threshold Adiabatic Logic

2018 Fiscal Year Final Research Report

• Project/Area Number: 17K14664
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Electron device/Electronic equipment
• Research Institution: Gifu University
• Principal Investigator: Takahashi Yasuhiro 岐阜大学, 工学部, 准教授 (00402214)
• Project Period (FY): 2017-04-01 – 2019-03-31
• Keywords: 断熱的論理 / サブスレッショルド論理 / 低電圧 / 低消費電力

Outline of Final Research Achievements

In this research, we present a new power consumption model of adiabatic sub-threshold logic circuit. To analyze the power model, at first, we measured our designed sub-threshold logic and then derived the power consumption model of that logic. Secondly, We tried to recalculate the power consumption through the model. From the results, we found that the adiabatic sub-threshold power model depends on the parasitic factor, that is internal capacitance and resistance. Finally, we show a new power consumption model.

Free Research Field

半導体集積回路設計

Academic Significance and Societal Importance of the Research Achievements

環境発電技術を用いたワイヤレスセンサネットワーク（WSN）に使用される集積回路の最小動作電圧と動作周波数の関係は、今まで明らかではなかった。本研究の結果から、低電圧で動作する論理回路の電力メカニズムが明らかになったことから、WSN用集積回路の電源電圧を限界まで低下することが可能となる。その結果、従来技術では不可能だった極低電圧および極低消費電力特性を有する新しいWSN用集積回路開発の契機につながると期待できる。