• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to project page

2009 Fiscal Year Final Research Report

Nano MOSFET Fluctuations and Device Integrity

Research Project

  • PDF
Project/Area Number 18063006
Research Category

Grant-in-Aid for Scientific Research on Priority Areas

Allocation TypeSingle-year Grants
Review Section Science and Engineering
Research InstitutionThe University of Tokyo

Principal Investigator

HIRAMOTO Toshiro  The University of Tokyo, 生産技術研究所, 教授 (20192718)

Co-Investigator(Renkei-kenkyūsha) SARAYA Takuya  東京大学, 生産技術研究所, 助手 (90334367)
Project Period (FY) 2006 – 2009
Keywords特性ばらつき / しきい値電圧 / SOI / SRAM
Research Abstract

Random variability has been studied by measurements and simulation. It has been clarified that SOI MOSFETs with very thin buried oxide is less sensitive to random dopant fluctuations. A new method of self-suppression of variability after chip fabrication has been proposed and its validity has been demonstrated by simulation.

  • Research Products

    (41 results)

All 2011 2010 2009 2008 2007 2006

All Journal Article (12 results) (of which Peer Reviewed: 12 results) Presentation (27 results) Book (1 results) Patent(Industrial Property Rights) (1 results)

  • [Journal Article] Threshold Voltage Dependence of Threshold Voltage Variability in Intrinsic Channel Silicon-on-Insulator2010

    • Author(s)
      C.Lee, A.T.Putra, K.Shimizu, T.Hiramoto
    • Journal Title

      No.4, Issue 2

      Pages: 04DC01

    • Peer Reviewed
  • [Journal Article] Impact of Oxide Thickness Fluctuation and Local Gate Depletion on Threshold Voltage Variation in Metal-Oxide-Semiconductor Field-Effect-Transistors2009

    • Author(s)
      A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, T.Hiramoto
    • Journal Title

      Japanese Journal of Applied Physics Vol.48, No.6

      Pages: 064504

    • Peer Reviewed
  • [Journal Article] MOSトランジスタのスケーリングに伴う特性ばらつき2009

    • Author(s)
      平本俊郎, 竹内潔, 西田彰男
    • Journal Title

      電子情報通信学会会誌 Vol.92, No.6

      Pages: 416-426

    • Peer Reviewed
  • [Journal Article] Consideration of Random Dopant Fluctuation Models for Accurate Prediction of Threshold Voltage Variation of Metal-Oxide-Semiconductor Field-Effect Transistors in 45nm Technology and Beyond2009

    • Author(s)
      A.T.Putra, A.Nishida, S.Kamohara, T.Tsunomura, T.Hiramoto
    • Journal Title

      Japanese Journal of Applied Physics Vol.48, No.4

      Pages: 044502

    • Peer Reviewed
  • [Journal Article] Random Threshold Voltage Variability Induced by Gate-Edge Fluctuations in Nanoscale Metal-Oxide-Semiconductor Field-Effect Transistors2009

    • Author(s)
      A.T.Putra, A.Nishida, S.Kamohara, T.Hiramoto
    • Journal Title

      Applied Physics Express Vol.2, No.2

      Pages: 024501

    • Peer Reviewed
  • [Journal Article] 増大する微細MOSトランジスタの特性ばらつき:現状と対策2008

    • Author(s)
      平本俊郎, 竹内潔, 西田彰男
    • Journal Title

      電気学会論文誌C Vol.128, No.6

      Pages: 820-824

    • Peer Reviewed
  • [Journal Article] Variable Body-Factor SOI MOSFET with Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control2008

    • Author(s)
      T.Ohtou, T.Saraya, T.Hiramoto
    • Journal Title

      IEEE Transactions on Electron Devices vol.54, no.1

      Pages: 40-46

    • Peer Reviewed
  • [Journal Article] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX2007

    • Author(s)
      T.Ohtou, N.Sugii, T.Hiramoto
    • Journal Title

      IEEE Electron Devices Letters Vol.28, No.8

      Pages: 740-742

    • Peer Reviewed
  • [Journal Article] Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations2007

    • Author(s)
      T.Hiramoto, T.Nagumo, T.Ohtou, K.Yokoyama
    • Journal Title

      IEICE Transactions on Electronics Vol.E90-C, No.4

      Pages: 836-841

    • Peer Reviewed
  • [Journal Article] Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme2007

    • Author(s)
      T.Ohtou, K.Yokoyama, K.Shimizu, T.Nagumo, T.Hiramoto
    • Journal Title

      IEEE Transactions on Electron Devices Vol.54, No.2

      Pages: 301-307

    • Peer Reviewed
  • [Journal Article] Design Guideline of Multi-Gate MOSFETs With Substrate-Bias Control2006

    • Author(s)
      T.Nagumo, T.Hiramoto
    • Journal Title

      IEEE Transactions on Electron Devices Vol.53, No.12

      Pages: 3025-3031

    • Peer Reviewed
  • [Journal Article] Modeling of Body Factor and Subthreshold Swing in Bulk Metal Oxide Semiconductor Field Effect Transistors in Short-Channel Regime2006

    • Author(s)
      A.T.Putra, M.Saitoh, G.Tsutsui, T.Hiramoto
    • Journal Title

      Japanese Journal of Applied Physics Vol.45, No.8A

      Pages: 6173-6176

    • Peer Reviewed
  • [Presentation] Statistical Comparison of Random Telegraph Noise (RTN) in Bulk and Fully Depleted SOI MOSFETs2011

    • Author(s)
      J.Nishimura, T.Saraya, T.Hiramoto
    • Organizer
      Ultimate Integration of Silicon (ULIS)
    • Place of Presentation
      Cork, Ireland
    • Year and Date
      2011-03-16
  • [Presentation] Measurements and characterization of statistical variability2010

    • Author(s)
      T.Hiramoto
    • Organizer
      Workshop on Simulation and Characterization of Statistical CMOS Variability and Reliability, The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
    • Place of Presentation
      Royal Hotel Carlton, Bologna, Italy
    • Year and Date
      2010-09-09
  • [Presentation] Effect of Back Bias on Variability in Intrinsic Channel SOI MOSFETs2010

    • Author(s)
      T.Hiramoto, T.Saraya, C.Lee
    • Organizer
      International Symposium on Technology Evolution for Silicon Nano-Electronics (ISTESNE)
    • Place of Presentation
      Tokyo Institute of Technology
    • Year and Date
      2010-06-03
  • [Presentation] Simultaneously improvement of Write and Static Noise Margins in SRAM by Post-Fabrication Self-Convergence Technique2010

    • Author(s)
      M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
    • Organizer
      Workshop "The Fruits of Variability Research in Europe", Design, Automation & Test in Europe (DATE)
    • Place of Presentation
      International Congress Centre in Dresden, Dresden, Germany
    • Year and Date
      2010-03-12
  • [Presentation] Variability research : accomplishments and future directions-a Japanese perspective2010

    • Author(s)
      T.Hiramoto
    • Organizer
      Workshop "The Fruits of Variability Research in Europe", Design, Automation & Test in Europe (DATE)
    • Place of Presentation
      International Congress Centre in Dresden, Dresden, Germany
    • Year and Date
      2010-03-12
  • [Presentation] Improvement of Static Noise Margin in SRAM by Post-Fabrication Self-Convergence Technique2009

    • Author(s)
      M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
    • Organizer
      International Semiconductor Device Research Symposium (ISDRS), TP7-03
    • Place of Presentation
      University of Maryland, MD, USA
    • Year and Date
      2009-12-10
  • [Presentation] Anomalous Back-Bias Dependence of Threshold Voltage Variability in NMOSFETs Due to High Concentration Regions near Source and Drain2009

    • Author(s)
      I.Yamato, T.Mama, T.Tsunomura, A.Nishida, T.Hiramoto
    • Organizer
      International Semiconductor Device Research Symposium (ISDRS), WP5-04
    • Place of Presentation
      University of Maryland, MD, USA
    • Year and Date
      2009-12-09
  • [Presentation] Vth Dependence of Vth Variability in Intrinsic Channel SOI MOSFETs with Ultra-Thin BOX2009

    • Author(s)
      C.Lee, A.T.Putra, K.Shimizu, T.Hiramoto
    • Organizer
      International Conference on Solid State Devices and Materials (SSDM)
    • Place of Presentation
      Sendai
    • Year and Date
      2009-10-07
  • [Presentation] Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors2009

    • Author(s)
      M.Suzuki, T.Saraya, K.Shimizu, T.Sakurai, T.Hiramoto
    • Organizer
      Symposium on VLSI Technology, pp.148-149
    • Place of Presentation
      Kyoto
    • Year and Date
      2009-06-16
  • [Presentation] A New Methodology for Evaluating VT Variability Considering Dopant Depth Profile2009

    • Author(s)
      A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, S.Inaba, K.Terada, T.Hiramoto
    • Organizer
      Symposium on VLSI Technology, pp.116-117
    • Place of Presentation
      Kyoto
    • Year and Date
      2009-06-16
  • [Presentation] Impact of Lateral Dopant Profile on Threshold Voltage Variability in Scaled MOSFETs2009

    • Author(s)
      I.Yamato, A.T.Putra, T.Hiramoto
    • Organizer
      Silicon Nanoelectronics Workshop, pp.35-36
    • Place of Presentation
      Kyoto
    • Year and Date
      2009-06-13
  • [Presentation] Characterization of CMOS Variability Utilizing 1M-DMA and Takeuchi Plot2008

    • Author(s)
      T.Hiramoto
    • Organizer
      Workshop on Test Structure Design for Variability Characterization
    • Place of Presentation
      DoulbleTree Hotel, San Jose, CA, USA
    • Year and Date
      2008-11-13
  • [Presentation] Measuring and Understanding Device Variability2008

    • Author(s)
      T.Hiramoto
    • Organizer
      ESSDER/ ESSIRC Variability Workshop
    • Place of Presentation
      Edinburgh International Conference Centre, Edinburgh, UK
    • Year and Date
      2008-09-19
  • [Presentation] Impact of Fixed Charge at MOSFETs' SiO2/Si Interface on Vth Variation2008

    • Author(s)
      A.T.Putra, T.Tsunomura, A.Nishida, S.Kamohara, K.Takeuchi, T.Hiramoto
    • Organizer
      International Conference on Simulation of Semiconductor Devices and Processes (SISPAD)
    • Place of Presentation
      Hakone Prince Hotel, Kanagawa, Japan
    • Year and Date
      2008-09-09
  • [Presentation] Mobility and Variability in Silicon Nanowire MOSFETs2008

    • Author(s)
      T.Hiramoto, M.Kobayashi, J.Chen
    • Organizer
      14th International Symposium on the Physics of Semiconductors and Applications (ISPSA-2008), p.192
    • Place of Presentation
      Korea, Ramada Plaza Jeju Hotel, Jeju
    • Year and Date
      2008-08-27
  • [Presentation] Impact of Atomic Oxide Roughness and Local Gate Depletion on Vth Variation in MOSFETs2008

    • Author(s)
      A.T.Putra, T.Tsunomura, A.Nishida , S.Kamohara, K.Takeuchi, T.Hiramoto
    • Organizer
      IEEE Silicon Nanoelectronics Workshop, S1205
    • Place of Presentation
      Hilton Hawaiian Village, HI, USA
    • Year and Date
      2008-06-15
  • [Presentation] FinFETs with Both Large Body Factor and High Drive-Current2007

    • Author(s)
      K.Takahashi, A.T.Putra, T.Hiramoto
    • Organizer
      International Semiconductor Device Research Symposium (ISDRS), WP9-01-11
    • Place of Presentation
      University of Maryland, MD, USA
    • Year and Date
      2007-12-12
  • [Presentation] Impact of Local Poly-Si Gate Depletion on Vth Variation in Nanoscale MOSFETs Investigated by 3D Device Simulation2007

    • Author(s)
      A.T.Putra, A.Nishida, S.Kamohara, T.Tsunomura, T.Hiramoto
    • Organizer
      International Semiconductor Device Research Symposium (ISDRS), WP8-03
    • Place of Presentation
      University of Maryland, MD, USA
    • Year and Date
      2007-12-12
  • [Presentation] Robust Design of Transistors : Present Status and Measures to Characteristic Variations2007

    • Author(s)
      T.Hiramoto
    • Organizer
      2007 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD 2007), pp.5-8
    • Place of Presentation
      Commodore Hotel Gyeongju Chosun, Korea
    • Year and Date
      2007-06-25
  • [Presentation] Body Factor and Leakage Current Reduction in Bulk FinFETs2007

    • Author(s)
      K.Takahashi, T.Ohtou, A.T.Putra, K.Shimizu, T.Hiramoto
    • Organizer
      Silicon Nanoelectronics Workshop, pp.95-97
    • Place of Presentation
      Rihga Royal Hotel Kyoto
    • Year and Date
      2007-06-10
  • [Presentation] Random Vth Variation Induced by Gate Edge Fluctuations in Nanoscale MOSFETs2007

    • Author(s)
      A.T.Putra, A.Nishida, S.Kamohara, T.Hiramoto
    • Organizer
      Silicon Nanoelectronics Workshop, pp.73-74
    • Place of Presentation
      Rihga Royal Hotel Kyoto
    • Year and Date
      2007-06-10
  • [Presentation] Characteristics Variation in Silicon Nanowire Transistors2007

    • Author(s)
      T.Hiramoto, M.Kobayashi
    • Organizer
      3rd International Nanotechnology Conference on Communication and Cooperation
    • Place of Presentation
      Brussels, Bergium
    • Year and Date
      2007-04-17
  • [Presentation] Experimental Demonstrations of Superior Characteristics of Variable Body-Factor (γ) Fully-Depleted SOI MOSFETs with Extremely Thin BOX of 10nm2006

    • Author(s)
      T.Ohtou, T.Saraya, K.Shimokawa, Y.Doumae, Y.Nagatomo, J.Ida, T.Hiramoto
    • Organizer
      IEEE International Electron Devices Meeting (IEDM), pp.877-880
    • Place of Presentation
      San Francisco, CA, USA
    • Year and Date
      2006-12-13
  • [Presentation] Experimental Study on Quantum Structure of Silicon Nano Wire and Its Impact on Nano Wire MOSFET and Single-Electron Transistor2006

    • Author(s)
      M.Kobayashi, T.Hiramoto
    • Organizer
      Technical Digests of IEEE International Electron Devices Meeting (IEDM), pp.1007-1009
    • Place of Presentation
      San Francisco, CA, USA
    • Year and Date
      2006-12-11
  • [Presentation] Critical Substrate Bias in Variable-Threshold Voltage CMOS with Short Channel FD SOI MOSFETs2006

    • Author(s)
      A.T.Putra, T.Ohtou, T.Hiramoto
    • Organizer
      IEEE Silicon Nanoelectronics Workshop, pp.159-160
    • Place of Presentation
      Honolulu, HI, USA
    • Year and Date
      2006-06-12
  • [Presentation] Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully-Depleted SOI MOSFETs with Extremely Thin BOX2006

    • Author(s)
      T.Ohtou, N.Sugii, T.Hiramoto
    • Organizer
      IEEE Silicon Nanoelectronics Workshop, pp.15-16
    • Place of Presentation
      Honolulu, HI, USA
    • Year and Date
      2006-06-11
  • [Presentation] Multi-Gate MOSFETs with Back-Gate Control2006

    • Author(s)
      T.Hiramoto, T.Nagumo
    • Organizer
      2006 International Conference on Integrated Circuit Design and Technology (ICICDT), pp.80-81
    • Place of Presentation
      Padova University, Padova, Italy
    • Year and Date
      2006-05-25
  • [Book] 集積ナノデバイス2009

    • Author(s)
      平本俊郎, 内田建, 竹内潔, 杉井信之
    • Total Pages
      199-221
    • Publisher
      丸善
  • [Patent(Industrial Property Rights)] ラッチ回路の電圧特性調整方法および半導体装置の電圧特性調整方法2009

    • Inventor(s)
      平本俊郎, 鈴木誠, 桜井貴康
    • Industrial Property Rights Holder
      東京大学
    • Industrial Property Number
      特許,特願2009-141510
    • Filing Date
      2009-06-12

URL: 

Published: 2012-02-13   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi