2009 Fiscal Year Final Research Report
Research of the reconfigurable processor for large-scale numerical computation
| Project/Area Number |
18300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
HIRONAKA Tetsuo Hiroshima City University, 情報科学研究科, 教授 (10253486)
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| Co-Investigator(Renkei-kenkyūsha) |
TANIGAWA Kazuya 広島市立大学, 情報科学研究科, 助教 (80382373)
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| Project Period (FY) |
2006 – 2009
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| Keywords | リコンフィギャラブルプロセッサ / 高精度数値計算 |
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| Research Abstract |
Scientific calculations such as Loop integrals and CG methods require multiple-precision floating-point operations. In this project, to achieve faster multiple-precision floating-point operations used in these applications, we propose HP-DSFP architecture. In HP-DSFP architecture, by using the digit-serial computation scheme, we achieved 2.4 times higher performance compared with the conventional arithmetic unit using the same chip area.
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