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2009 Fiscal Year Final Research Report

Research on vertical InP-related hot electron transistors with insulated gate

Research Project

  • PDF
Project/Area Number 19206038
Research Category

Grant-in-Aid for Scientific Research (A)

Allocation TypeSingle-year Grants
Section一般
Research Field Electron device/Electronic equipment
Research InstitutionTokyo Institute of Technology

Principal Investigator

MIYAMOTO Yasuyuki  Tokyo Institute of Technology, 大学院・理工学研究科, 准教授 (40209953)

Project Period (FY) 2007 – 2009
Keywordsホットエレクトロン / 電子ランチャー / InP / InGaAs / 電子ビーム露光 / III-V MOS / バリスティック電子 / モンテカルロシミュレーション / 縦型電子デバイス
Research Abstract

High current density (6MA/cm^2) that was important for high speed operation was achieved by using a 15-nm-wide source that was narrowest in compound semiconductor vertical transistors. Moreover, the current drivability without dependence of channel length was confirmed and suggested that electron transportation in the channel was ballistic. High-k dielectric for high drivability and regrown source for extension of the scheme in lateral device were also studied.

  • Research Products

    (22 results)

All 2010 2009 2008 2007 Other

All Journal Article (5 results) (of which Peer Reviewed: 5 results) Presentation (13 results) Book (1 results) Remarks (1 results) Patent(Industrial Property Rights) (2 results)

  • [Journal Article] Estimation of collector current spreading in InGaAs SHBT having 75-nm-thick collector2010

    • Author(s)
      Y. Miyamoto, S. Takahashi, T. Kobayashi, H. Suzuzki, K. Furuya
    • Journal Title

      IEICE TRANSACTIONS on Electronics vol.E-93C

      Pages: 644-647

    • Peer Reviewed
  • [Journal Article] Monte Carlo Analysis of Base Transit Times of InP/GaInAs Heterojunction Bipolar Transistors with Ultra thin Graded Bases2010

    • Author(s)
      T. Uesawa, M. Yamada, Y. Miyamoto, K. Furuya
    • Journal Title

      Jpn. J. Appl. Phys vol.49

      Pages: 024302

    • Peer Reviewed
  • [Journal Article] Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance, High Voltage Gain2009

    • Author(s)
      H. Saito, Y. Miyamoto, K. Furuya
    • Journal Title

      Applied Physics Express 巻2

      Pages: 03451

    • Peer Reviewed
  • [Journal Article] Cutoff Frequency Characteristics of Gate-Control Hot Electron Transistors by Monte Carlo Simulation2008

    • Author(s)
      M. Igarashi, K. Furuya, Y. Miyamoto
    • Journal Title

      Physica Statu s Solidi(C) 巻5

      Pages: 70-73

    • Peer Reviewed
  • [Journal Article] InP/InGaAs hot electron transistors with insulated gate2007

    • Author(s)
      A. Suwa, T. Hasegawa, T. Hino, H. Sa ito, M. Oono, Y. Miyamoto, K. Furuya
    • Journal Title

      Jpn. J. Appl. Phys 巻46

      Pages: L617-L619

    • Peer Reviewed
  • [Presentation] Submicron InP/InGaAs composite channel MOSFETs with selectively regrown n+-source/drain buried into channel undercut2010

    • Author(s)
      T. Kanazawa, K. Wakabayashi, H. Saito, R. Terao, T. Tajima, S. Ikeda, Y. Miyamoto, K. Furuya
    • Organizer
      22nd Int. Conf. Indium Phosphide and Related Materials (IPRM20 10)
    • Place of Presentation
      香川県高松市
    • Year and Date
      2010-06-02
  • [Presentation] Selective undercut etching for ultra narrow mesa structure in vertical InGaA s channel MISFET2010

    • Author(s)
      H. Saito, Y. Miyamoto, K. Furuya
    • Organizer
      22nd Int. Conf. Indium Phosphide and Related Materials (IPRM20 10)
    • Place of Presentation
      香川県高松市
    • Year and Date
      2010-06-02
  • [Presentation] テラヘルツ帯におけるトランジスタ2010

    • Author(s)
      宮本恭幸
    • Organizer
      応用電子物性分科会研究例会
    • Place of Presentation
      東京
    • Year and Date
      2010-01-29
  • [Presentation] InGaAs/InP MISFET (Invited)2009

    • Author(s)
      Y. Miyamoto
    • Organizer
      Int. Symposium on Silicon Nano Devices in 2030
    • Place of Presentation
      東京
    • Year and Date
      2009-10-14
  • [Presentation] Fabrication of InP/InGaAs Undoped Channel MOSFET with Selectivel y Regrown N+-InGaAs Source Region2009

    • Author(s)
      T. Kanazawa
    • Organizer
      2009 Int. Conf. Solid State Devices and Materi als (SSDM 2009)
    • Place of Presentation
      宮城県仙台市
    • Year and Date
      2009-10-07
  • [Presentation] InGaAs/InP MISFET with ep itaxially grown source (Invited)2009

    • Author(s)
      Y. Miyamoto
    • Organizer
      2009 A sia-Pacific Workshop on Fundamentals an d Applications of Advanced Semiconducto r Devices (AWAD)
    • Place of Presentation
      Busan, Korea
    • Year and Date
      2009-06-25
  • [Presentation] InP/InGaAs-channel MOSFET with MOVPE Selective Regrown Source2009

    • Author(s)
      T. Kanazawa
    • Organizer
      21 st Int. Conf. Indium Phosphide and Rela ted Materials (IPRM2009)
    • Place of Presentation
      Newport Beach, USA
    • Year and Date
      2009-05-13
  • [Presentation] Vertical InGaAs MOSFET with Hetero-Launcher and Undoped Channe2009

    • Author(s)
      H. Saito
    • Organizer
      21st Int. Conf. Indium Phosphide and Related Materials (IPRM2009)
    • Place of Presentation
      Newport Beach, USA
    • Year and Date
      2009-05-13
  • [Presentation] InGaAs MISFET with hetero-laucher (Invited)2009

    • Author(s)
      Y. Miyamoto
    • Organizer
      2009 RCIQE International Seminar on "Advanced Semiconductor Materials and Devices"
    • Place of Presentation
      北海道札幌市
    • Year and Date
      2009-03-03
  • [Presentation] Lateral Buried Growth of N+-InGaAs Source/Drain Region to Undercut InGaAs Channel Structure for High Drive Current N-type MOSFET2008

    • Author(s)
      T. Kanazawa, H. Saito, K. Wakabayashi, Y. Miyamoto, K. Furuya
    • Organizer
      2008 Int. Conf. Solid State Devices and Materials (SSDM2008)
    • Place of Presentation
      茨城県つくば市
    • Year and Date
      2008-09-24
  • [Presentation] Hot electron transistor controlled by insulated gate with 70nm-wide emitter2008

    • Author(s)
      H. Saito, T. Hino, Y. Miyamoto, K. Furuya
    • Organizer
      20th Int. Conf. Indium Phosphide and Related Materials (IPRM2008)
    • Place of Presentation
      Versailles, France
    • Year and Date
      2008-05-26
  • [Presentation] InP系バリスティックトランジスタ2008

    • Author(s)
      宮本恭幸、古屋一仁
    • Organizer
      電子情報通信学会電子デバイス研究会
    • Place of Presentation
      北海道札幌市
    • Year and Date
      2008-01-30
  • [Presentation] Fabrication of hot electron transistors controlled by insulated gate2007

    • Author(s)
      T. Hino, A. Suwa, T. Hasegawa, H. Saito, M. Oono, Y. Miyamoto, K. Furuya
    • Organizer
      19th Int. Conf. Indium Phosphide and Related Materials (IPRM2007)
    • Place of Presentation
      島根県松江市
    • Year and Date
      2007-05-15
  • [Book] 電子デバイス2009

    • Author(s)
      宮本恭幸
    • Total Pages
      153
    • Publisher
      培風館
  • [Remarks] ホームページ等

    • URL

      http://www.pe.titech.ac.jp/Furuya-MiyamotoLab/index.htm

  • [Patent(Industrial Property Rights)] 半導体装置の製造方法

    • Inventor(s)
      井田実、山幡章司、齋藤尚史、宮本恭幸
    • Industrial Property Rights Holder
      日本電信電話、東京工業大学
    • Industrial Property Number
      特許特願2010-100797
  • [Patent(Industrial Property Rights)] ホットエレクトロントランジスタ、及びその製造方法

    • Inventor(s)
      宮本恭幸、前田寛、竹内克彦
    • Industrial Property Rights Holder
      東京工業大学
    • Industrial Property Number
      特許第4354192号

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Published: 2011-06-18   Modified: 2016-04-21  

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