2009 Fiscal Year Final Research Report
Dependable VLSI design methodology which conquers engineering limits due to shrinking device size
| Project/Area Number |
19300009
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
NANYA Takashi The University of Tokyo, 先端科学技術研究センター, 教授 (80143684)
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| Co-Investigator(Kenkyū-buntansha) |
IMAI Masahi 東京大学, 駒場オープンラボラトリー, 特任准教授 (70323665)
KONDO Masaaki 電気通信大学, 大学院・情報システム学研究科, 准教授 (30376660)
KAMIYAMA Kazuto 電気通信大学, 電気通信学部, 特任助教 (60447331)
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| Project Period (FY) |
2007 – 2009
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| Keywords | 計算機システム / 半導体超微細化 / ディペンダブルVLSI |
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| Research Abstract |
It has been recognized that a lot of problems like leakage current, delay variations, and soft-error become more serious due to shrinking device size in VLSI. In this research, we have developed an asynchronous design methodology which can tolerate any timing-related problems using the energy-efficient coding and the multi-threshold-voltage transistors. We have also developed a processor-level fault tolerance technique for dependable chip multiprocessors which will be widely used in the future technology.
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