2009 Fiscal Year Final Research Report
Designing of Ultra High-Speed and Compact Variable Latency PipelinedArithmetic Units
| Project/Area Number |
19700037
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Tohoku University |
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Principal Investigator |
EGAWA Ryusuke Tohoku University, サイバーサイエンスセンター, 助教 (80374990)
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| Project Period (FY) |
2007 – 2009
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| Keywords | ウェーブパイプライン / VLSI / 回路設計 / 熱解析 / 等遅延回路 |
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| Research Abstract |
To realize low-power and high-speed arithmetic units with future CMOS technologies, this project focused on and carried out research that concerned with a circuit compaction technique and a delay balancing technique. An input bit-sliced circuit partitioning method for circuit scale compaction and a delay balancing methods based on logical effort theory for wave pipelines have been proposed and evaluated. The experimental results clarified the effective of both proposals.
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