4T LT poly-Si TFT with NC technology on glass substrate for low-cost IoT devices

2021 Fiscal Year Final Research Report

• Project/Area Number: 19K04534
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Review Section: Basic Section 21060:Electron device and electronic equipment-related
• Research Institution: Tohoku Gakuin University
• Principal Investigator: HARA Akito 東北学院大学, 工学部, 教授 (20417398)
• Co-Investigator(Kenkyū-buntansha): 鈴木 仁志 東北学院大学, 工学部, 准教授 (70351319)
• Project Period (FY): 2019-04-01 – 2022-03-31
• Keywords: 薄膜トランジスタ / 多結晶シリコン / 多結晶ゲルマニウム / 高誘電体 / 強誘電体

Outline of Final Research Achievements

A CMOS inverter was fabricated using four-terminal (4T) poly-Si TFTs with high-k HfO2 gate dielectric. To operate CMOS inverters at low VDD voltages, it is necessary to control the threshold voltage (Vth). In this study, a 4T structure was used to control Vth, and the gate width of the p-channel was designed to be three times that of the n-channel to balance the on-current. A CMOS inverter with a logic threshold of 0.5 V and a gain of 14 at VDD = 1.0 V was designed successfully. In addition, we successfully operated Cu-MIC 4T poly-GeSn TFTs using HfO2 on a glass substrate.
Ferroelectric HfZrO2 was fabricated using a single target sputtering system. Although ferroelectricity was observed in the RTA thin film, it was weak. This is due to the formation of an additional oxide layer at the interface.

Free Research Field

半導体工学

Academic Significance and Societal Importance of the Research Achievements

IoTエッジデバイスをシリコン以外の基板上に形成する技術は、IoTエッジデバイスの多様化・多機能化とともに今後重要になる。代表者が独自開発した高移動度を有する４端子低温多結晶シリコンTFTに対して負性容量技術を融合することで、高移動度(>300 cm2/Vs)・精密Vth制御・小さいs値(<100 mV/dec)の3要素全てを満足させ、Vdd=1.0 Vでgain>10を有するCMOSインバータを安価ガラス基板上で実現することを目指した。これにより、安価ガラス基板上に低価格・低消費電力IoTエッジデバイスを実現するためのデバイス・イノベーションを実現する。