A low-power direct-RF sampling receiver for IoT wireless applications

2021 Fiscal Year Final Research Report

• Project/Area Number: 19K11890
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Review Section: Basic Section 60040:Computer system-related
• Research Institution: Osaka Institute of Technology
• Principal Investigator: Kihara Takao 大阪工業大学, 工学部, 准教授 (10736458)
• Project Period (FY): 2019-04-01 – 2022-03-31
• Keywords: 直接RFサンプリング受信機 / 時間インターリーブA/D変換器 / デジタル補正 / 電圧制御発振器

Outline of Final Research Achievements

1. We designed a time-interleaved analog-to-digital converter (TI-ADC), receiver, and digital corrections on Simulink. The correction removed the mismatch aliasing signals, and harmonic distortion (HD) and intermodulation (IM) products owing to the 3rd-order nonlinearity of the ADC. Simulations showed that the correction improved the two-tone spurious-free dynamic range (SFDR) of a TI-ADC with a sampling frequency of 3,680 MHz from 54.8 dB to 66.7 dB.
2. We synthesized, placed and routed the receiver with voltage controlled oscillators (VCOs) of the TI-ADC by using a design kit of 65-nm CMOS technology. Simulations showed that we decreased the power consumption of the digital circuit from 15.3 mW to 6.9 mW by changing the decimation number from eight to two.
3. We reported these results in one journal paper (IEEE) and four conference proceedings (IEEE, peer-reviewed).

Free Research Field

集積回路設計

Academic Significance and Societal Importance of the Research Achievements

時間インターリーブA/D変換器から生じる2種類の不要波（チャネルミスマッチと3次歪み)を同時にデジタル補正（信号処理）で低減した結果はこれまでになく、本研究の成果は学術的に非常に意義がある。さらに、直接RFサンプリング受信機（GS/s動作）のデジタル回路をこれほどの低消費電力（6.9 mW）で動作させた報告もこれまでにない。本受信機の集積回路（IC）が実用化されれば、無線機器のさらなる普及につながるので、社会的意義も非常に大きい。