2010 Fiscal Year Final Research Report
Basic Studies on Testability and Security for Network-on-Chip
| Project/Area Number |
20300018
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
FUJIWARA Hideo Nara Institute of Science and Technology, 情報科学研究科, 教授 (70029346)
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| Co-Investigator(Kenkyū-buntansha) |
INOUE Michiko 奈良先端科学技術大学院大学, 情報科学研究科, 准教授 (30273840)
OHTAKE Satoshi 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20314528)
YONEDA Tomokazu 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871)
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| Project Period (FY) |
2008 – 2010
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| Keywords | VLSI設計技術 / VLSIのテスト / ネットワークオンチップ / テスト容易性 / 安全性(セキュリティ) / スキャン設計 |
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| Research Abstract |
(1) We proposed a design-for-test method for functional RTL circuits (called F-Scan) and showed the effectiveness by using benchmarks. (2) We proposed an ATPG and DFT method for asynchronous circuits used in Network-on-Chip. (3) We introduced a new concept of shift-register equivalence and proposed a secure scan method that satisfies both testability and security and clarified the security level analytically.
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