2010 Fiscal Year Final Research Report

HDL Logic Circuit Design Laboratory in Tokyo National College of Technology

Research Project

Project/Area Number	20500765
Research Category	Grant-in-Aid for Scientific Research (C)
Allocation Type	Single-year Grants
Section	一般
Research Field	Science education
Research Institution	Tokyo National College of Technology
Principal Investigator	KAGE Tetsuro Tokyo National College of Technology, 電子工学科, 教授 (30390420)
Co-Investigator(Kenkyū-buntansha)	OHTSUKA Tomohiko 東京工業高等専門学校, 電子工学科, 教授 (80262278) KOIKE Kiyoyuki 東京工業高等専門学校, 電子工学科, 教授 (20283038) YUGA Masamitsu 東京工業高等専門学校, 電子工学科, 教授 (40123997) AOKI Hiroyuki 東京工業高等専門学校, 電子工学科, 教授 (20249759)
Project Period (FY)	2008 – 2010
Keywords	工学教育 / LSI設計技術教育
Research Abstract	HDL (Hardware Description Language) is essential for developing industrial LSI's. We have included an HDL logic circuit design laboratory in our experimental program for electronic engineering course students. Designed logic circuits by the students in HDL are configured on an FPGA (Field Programmable Gate Array) on the spot. The students have filled out questionnaires on HDL design experience. The paper reports our HDL logic circuit design laboratory, and tallies up the questionnaires.

(3 results)