2009 Fiscal Year Final Research Report
A Study on False Negative Reduction on Formal Verification of Logic Circuits
| Project/Area Number |
20700046
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Nagoya University |
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Principal Investigator |
NAKAMURA Kazuhiro Nagoya University, 大学院・情報科学研究科, 助教 (90335076)
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| Project Period (FY) |
2008 – 2009
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| Research Abstract |
A reducing method of false nagatives on formal verification of sequential circuits with a circuit conversion is developed. In addition to the method, multi time-frame state reduction for accelerating sequential SAT is developed.
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