Synthesizable Mixed-Signal Integrated Circuits for Agile Development of Analog AI Sensor Nodes

2021 Fiscal Year Final Research Report

• Project/Area Number: 20K14786
• Research Category: Grant-in-Aid for Early-Career Scientists
• Allocation Type: Multi-year Fund
• Review Section: Basic Section 21060:Electron device and electronic equipment-related
• Research Institution: The University of Tokyo
• Principal Investigator: Xu Zule 東京大学, 大学院工学系研究科(工学部), 特任講師 (50778925)
• Project Period (FY): 2020-04-01 – 2022-03-31
• Keywords: 自動配置配線可能なアナログ回路

Outline of Final Research Achievements

1) An 8-bit synthesizable ADC was designed, implemented, and verified with post-layout simulation. Its paper with verification result was accepted by IEEE TVLSI. 2) The proposed MOS capacitor and the related comparator were analyzed, and their analysis papers were accepted by Springer and JJAP, respectively. 3) A synthesizable PLL was realized and evaluated on silicon. Its paper was accepted by IEEE A-SSCC and was invited to IEEE JSSC (being reviewed). 4) Techniques proposed and developed in this research were employed to other types of PLLs. Two papers were accepted by the top-level conference IEEE VLSIC.

Free Research Field

電子デバイスおよび電子機器関連

Academic Significance and Societal Importance of the Research Achievements

進展しているスマート社会において、集積回路の多品種化とその研究開発の大規模化が見通され、本研究の成果により、センサーノードにおける重要かつ複雑なADC・PLL回路の開発時間の大幅な短縮を期待でき、集積回路開発の高速化・低コスト化、および少人数チームでもイノベーションの加速を貢献する。学術的意義については、自動配置配線可能なアナログ回路における主な課題は、配置配線による予測不可能な寄生素子が生じ、アナログ回路の線形性に大きく劣化させるということである。この課題に対し、本研究ではADCおよびPLLに様々な新規手法を提案・実証して結果を発表した。