2012 Fiscal Year Final Research Report
Investigation of True Scalable CMOS Integrated Circuit
| Project/Area Number |
21246056
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MASU Kazuya 東京工業大学, ソリューション研究機構, 教授 (20157192)
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| Project Period (FY) |
2009 – 2012
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| Keywords | 電子デバイス / 集積回路 / スケーリング |
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| Research Abstract |
Scaling of Si CMOS has been brought the performance improvement and low cost at the same time for long time. It is recognized that low cost is originated from the reduction of chip area, i.e., circuit area. When the high performance circuit is designed using the advanced CMOS process, if the chip area is not reduced, the design is not meaningful in the economical viewpoint． In this project, we have engaged in the design of digital and RF CMOS circuit, which has the scalability, i.e., the circuit which is designed using the advance CMOS process has the higher performance and the circuit area reduction at the same time. These results has been supported by the CMOS circuit design, fabrication and evaluation using 180nm, 90nm, 65nm and 40nm CMOS.
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