2012 Fiscal Year Final Research Report
On Establishment of General Synchronous Circuit Design Methodology to Enhance Delay Variation Robustness
| Project/Area Number |
21300012
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Tokyo Institute of Technology (2012)
Osaka University (2009-2011) |
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Principal Investigator |
TAKAHASHI Atsushi 東京工業大学, 大学院・理工学研究科, 准教授 (30236260)
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| Project Period (FY) |
2009 – 2012
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| Keywords | VLSI設計技術 / 同期回路 / 耐遅延変動特性 / 遅延エラー検出回復方式 / 可変 レイテンシ回路 |
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| Research Abstract |
In order to establish new design methodology that enable us to design and manufacture high-performance and high-reliable integrated circuits, a fast delay distribution estimation method that has enough accuracy was developed. Also, performance and performance improvement ratio of variable latency circuits in which delay error detection/correction mechanism is used were evaluated for various circuit, and a guideline to synthesize high-performance and high-reliable integrated circuits efficiently was obtained.
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