2011 Fiscal Year Final Research Report
Evaluation of Low-Cost Circuit-level Techniques to Compensate Temporal Errors.
| Project/Area Number |
21300014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto Institute of Technology |
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Principal Investigator |
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| Project Period (FY) |
2009 – 2011
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| Keywords | 一時故障 / VLSI / 信頼性 |
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| Research Abstract |
We investigate the low-cost circuit technique to mitigate temporal soft errors caused by neutrons and alpha particles. We mainly focus on redundant flip-flops(FFs) and sensors to detect temporal errors. We developed a redundant FF called BCDMR which is 100x stronger than normal non-redundant FFs and also sensor circuit to detect multiple cell upsets(MCUs) to upset redundant FFs.
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