2013 Fiscal Year Final Research Report
SET Immune Spaceborne LSI Circuit Designs by Embedding Cascade Voltage Switch Logic Circuits, High-speed Gates, and Neuron MOS structures
| Project/Area Number |
21560375
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Shizuoka Institute of Science and Technology |
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Principal Investigator |
HATANO Hiroshi 静岡理工科大学, 理工学部, 教授 (80238013)
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| Project Period (FY) |
2009-04-01 – 2014-03-31
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| Keywords | 電子デバイス・機器 / デバイス設計、シミュレーション / 放射線、粒子線、宇宙線 |
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| Research Abstract |
Single event tolerant spaceborne LSI circuits have been designed by embedding cascade voltage switch logic (CVSL) circuits, high-speed gates, and neuron MOS structures.
Single event transient (SET) effects on CVSL circuits have been investigated using SPICE. Static CVSL and clocked CVSL (C2VSL) circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. A CVSL half adder, a C2VSL half adder and a C2VSL full adder have confirmed to function correctly by the chip measurements. SET simulation results have confirmed that the CVSL and C2VSL circuits have increased tolerance to SET. SET tolerance for the CVSL and C2VSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL and C2VSL circuits are candidates for a SET tolerant spaceborne circuit. CVSL circuits are more than 200 times harder and C2VSL circuits are ten times harder than conventional CMOS circuits.
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