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2011 Fiscal Year Final Research Report

Study on robust circuit design techniques based on physical parameters of semiconductor devices and its Applications

Research Project

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Project/Area Number 21680004
Research Category

Grant-in-Aid for Young Scientists (A)

Allocation TypeSingle-year Grants
Research Field Computer system/Network
Research InstitutionKobe University

Principal Investigator

HIROSE Tetsuya  神戸大学, 大学院・工学研究科, 准教授 (70396315)

Project Period (FY) 2009 – 2011
KeywordsVLSI設計技術
Research Abstract

In this study, we developed analog and digital circuit design techniques that are tolerant to process and temperature variations. By developing ultra-low power current reference circuit, we can monitor the condition of threshold voltage of MOSFET in each LSI chip. We also proposed compensation architecture of digital circuits by using on-chip variation monitoring circuit. Moreover, we developed robust operational amplifier and comparator circuit that are fundamental analog circuit building blocks. For analog and digital signal processing systems, clock reference circuit and analog-digital converter were investigated. We demonstrated that these circuits operate robustly against process and temperature variations.

  • Research Products

    (25 results)

All 2012 2011 2010 2009 Other

All Journal Article (5 results) (of which Peer Reviewed: 5 results) Presentation (18 results) Remarks (1 results) Patent(Industrial Property Rights) (1 results)

  • [Journal Article] A Low-Power Level Shifter with Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs2012

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, and M. Numa
    • Journal Title

      IEEE Journal of Solid-State Circuits

      Volume: (in press)

    • Peer Reviewed
  • [Journal Article] Robust subthreshold CMOS digital circuit design with on-chip adaptive supply voltage scaling technique2011

    • Author(s)
      Y. Osaki, T. Hirose, K. Matsumoto, N. Kuroki, and M. Numa
    • Journal Title

      IEICE Transactions on Electronics

      Volume: vol.E94-C, no.1 Pages: 80-88

    • Peer Reviewed
  • [Journal Article] Temperature-compensated Nano-Ampere Current Reference Circuit with Subthreshold Metal-Oxide-Semiconductor Field Effect Transistor Resistor Ladder2011

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, and M. Numa
    • Journal Title

      Japanese Journal of Applied Physics

      Volume: vol.50, no.4 Pages: 04DE08-1-04DE08-6

    • Peer Reviewed
  • [Journal Article] Subthreshold SRAM with Write Assist Technique by Using On-Chip Threshold Voltage Monitoring Circuit2011

    • Author(s)
      K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa
    • Journal Title

      IEICE Transactions on Electronics

      Volume: vol.E94-C, no.6 Pages: 1042-1048

    • Peer Reviewed
  • [Journal Article] A Wide Input Voltage Range Level Shifter Circuit for Extremely Low-Voltage Digital LSIs2011

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, and M. Numa
    • Journal Title

      IEICE Electronics Express

      Volume: vol.8, no.12 Pages: 890-896

    • Peer Reviewed
  • [Presentation] A delay control technique for low-voltage subthreshold CMOS digital circuits2012

    • Author(s)
      S. Shiga, T. Hirose, Y. Osaki, N. Kuroki, and M. Numa
    • Organizer
      The 17th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI)
    • Place of Presentation
      Beppu, Japan
    • Year and Date
      2012-03-09
  • [Presentation] Ultra-Low Power and Low Voltage Circuit Design for Next-Generation Power-Aware LSI Applications2011

    • Author(s)
      T. Hirose
    • Organizer
      International SoC Conference 2011
    • Place of Presentation
      Jeju, Korea
    • Year and Date
      20111117-18
  • [Presentation] A 18. 9-nA Standby Current Comparator with Adaptive Bias Current Generator2011

    • Author(s)
      K. Isono, T. Hirose, K. Tsubaki, N. Kuroki, M. Numa
    • Organizer
      Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2011
    • Place of Presentation
      Jeju, Korea
    • Year and Date
      20111114-16
  • [Presentation] A 105-nW CMOS Thermal Sensor for Power-Aware Applications2011

    • Author(s)
      T. Nagayama, T. Hirose, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      10th IEEE Conference on Sensors
    • Place of Presentation
      Limerick, Ireland
    • Year and Date
      20111028-31
  • [Presentation] Current Compensation Circuit for Precise Nano-Ampere Current Reference2011

    • Author(s)
      K. Isono, T. Hirose, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      Extended abstract of the 2011 International Conference on Solid State Devices and Materials
    • Place of Presentation
      Nagoya, Japan
    • Year and Date
      20110928-30
  • [Presentation] A Level Shifter with Logic Error Correction Circuit for Extremely Low-Voltage Digital CMOS LSIs2011

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, M. Numa
    • Organizer
      37th IEEE European Solid-State Circuits Conference(ESSCIRC)
    • Place of Presentation
      Helsinki, Finland
    • Year and Date
      20110912-16
  • [Presentation] High Current Efficiency Sense Amplifier Using Body-Bias Control for Ultra-Low-Voltage SRAM2011

    • Author(s)
      C. Masuda, T. Hirose, K. Matsumoto, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      54th IEEE International Midwest Symposium on Circuits and Systems(MWSCAS)
    • Place of Presentation
      Souel, Korea
    • Year and Date
      20110807-10
  • [Presentation] A Level Shifter Circuit Design by Using Input/Output Voltage Monitoring Technique for Ultra-Low Voltage Digital CMOS LSIs2011

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, M. Numa
    • Organizer
      9th IEEE International NEWCAS conference
    • Place of Presentation
      Bordeaux, France
    • Year and Date
      20110626-29
  • [Presentation] A 95-nA, 523ppm/C, 0. 6-uW CMOS Current Reference Circuit with Subthreshold MOS Resistor Ladder2011

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, M. Numa
    • Organizer
      The 16th Asia and South Pacific Design Automation Conference
    • Place of Presentation
      Yokohama, Japan
    • Year and Date
      20110125-28
  • [Presentation] An on-chip delay compensation for nano-power subthreshold CMOS digital LSIs2010

    • Author(s)
      Y. Osaki, T. Hirose, K. Matsumoto, T. Tsujikawa, K. Tsubaki, N. Kuroki, M. Numa
    • Organizer
      Workshop on Information, Nano and Photonics Technology 2009
    • Place of Presentation
      WINPTech2009
    • Year and Date
      20101200
  • [Presentation] A CMOS Bandgap and Sub-Bandgap Voltage Reference Circuits for Nanowatt Power LSIs2010

    • Author(s)
      T. Hirose, K. Ueno, N. Kuroki, M. Numa
    • Organizer
      Proc. of Tech. Papers, IEEE Asian Solid-State Circuits Conference 2010
    • Place of Presentation
      Beijing, China
    • Year and Date
      20101108-10
  • [Presentation] Temperature Compensated Nano-Ampere CMOS Current Reference Circuit Using Small Offset Voltage2010

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, M. Numa
    • Organizer
      Extended abstract of the 2010 International Conference on Solid State Devices and Materials
    • Place of Presentation
      Tokyo, Japan
    • Year and Date
      20100922-24
  • [Presentation] A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities2010

    • Author(s)
      T. Hirose, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      The 36th European Solid-State Circuits Conference
    • Place of Presentation
      Sevilla, Spain
    • Year and Date
      20100914-16
  • [Presentation] Write-Assisted Subthreshold SRAM by Using On-Chip Threshold Voltage Monitoring Circuit2010

    • Author(s)
      K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      2010 IEEE International 53rd Midwest Symposium on Circuits and Systems
    • Place of Presentation
      Seattle
    • Year and Date
      20100801-04
  • [Presentation] Reference Circuit Design for Nano-Power Subthreshold CMOS LSIs2010

    • Author(s)
      T. Hirose
    • Organizer
      2010 CMOS Emerging Technologies Workshop
    • Place of Presentation
      Whistler, BC, CANADA
    • Year and Date
      20100500
  • [Presentation] Nano-Ampere CMOS Current Reference with Little Temperature Dependence Using Small Offset Voltage2010

    • Author(s)
      Y. Osaki, T. Hirose, N. Kuroki, M. Numa
    • Organizer
      2010 IEEE International 53rd Midwest Symposium on Circuits and Systems
    • Place of Presentation
      Seattle
    • Year and Date
      20100101-04
  • [Presentation] Variation Tolerant Subthreshold Adder Design for Ultra-low Power LSIs2009

    • Author(s)
      Y. Osaki, T. Hirose, K. Matsumoto, N. Kuroki, M. Numa
    • Organizer
      The 35th European Solid-State Circuits Conference
    • Place of Presentation
      Athens, Greece
    • Year and Date
      20090900
  • [Presentation] Switching-voltage detection and compensation circuits for ultra-low-voltage CMOS inverters, Delay-compensation techniques for ultra-low-power subthreshold CMOS digital LSIs2009

    • Author(s)
      K. Matsumoto, T. Hirose, Y. Osaki, N. Kuroki, M. Numa
    • Organizer
      52nd IEEE International Midwest Symposium on Circuits and Systems
    • Year and Date
      20090800
  • [Remarks]

    • URL

      http://cas.eedept.kobe-u.ac.jp

  • [Patent(Industrial Property Rights)] コンパレータ回路2011

    • Inventor(s)
      廣瀬哲也,椿啓志,磯野航輔
    • Industrial Property Rights Holder
      神戸大学
    • Industrial Property Number
      特許、特願2011-209587
    • Filing Date
      2011-09-26

URL: 

Published: 2013-07-31  

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