2011 Fiscal Year Final Research Report
Energy Optimization for Asynchronous Circuits using Freedom of Execution Speed
| Project/Area Number |
21700062
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Aizu |
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Principal Investigator |
SAITO Hiroshi 会津大学, コンピュータ理工学部, 准教授 (50361671)
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| Project Period (FY) |
2009 – 2011
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| Keywords | 非同期式回路 / 低消費エネルギー / 動作合成 / プロセッサ |
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| Research Abstract |
In this research, we optimize asynchronous circuits in terms of energy consumption using freedom of execution speed. Different from synchronous circuits where execution timing of all operations is decided by a global clock signal, execution timing of each operation in asynchronous circuits can be decided freely. Using this freedom, energy optimization is carried out. The result of this research is classified into two sub result. The first is for specific circuits and the second is for processor. For specific circuits, we proposed an energy optimization method. For given behavioral description of an application, latency constraint, and resource library, the proposed method calculates slack for each operation defined for the start time during behavioral synthesis. Then, slow circuits are allocated to operations which have slack. For processor, we designed an asynchronous AVR processor aimed for FPGA and ASIC implementations. Also, for energy optimization, we proposed area optimization and performance optimization methods. Comparing to synchronous AVR processor, the energy consumption of our asynchronous AVR processor was half of the synchronous one.
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