Study on fabrication process of 3-D structured MOS transistor having atomically flat gate insulator/Si interface

2014 Fiscal Year Final Research Report

• Project/Area Number: 22000010
• Research Category: Grant-in-Aid for Specially Promoted Research
• Allocation Type: Single-year Grants
• Review Section: Science and Engineering; Engineering
• Research Institution: Tohoku University
• Principal Investigator: OHMI Tadahiro 東北大学, 未来科学技術共同研究センター, 名誉教授 (20016463)
• Co-Investigator(Kenkyū-buntansha): HIRAYAMA Masaki 東北大学, 未来科学技術共同研究センター, 准教授 (70250701) ; GOTO Tetsuya 東北大学, 未来科学技術共同研究センター, 准教授 (00359556) ; SUWA Tomoyuki 東北大学, 未来科学技術共同研究センター, 助教 (70431541)
• Project Period (FY): 2010-04-21 – 2015-03-31
• Keywords: シリコン / MOSFET / LSI / 半導体製造プロセス / 半導体製造装置

Outline of Final Research Achievements

In this study, the atomically flattening technology of any crystalline silicon surface was developed ; in the result the electrical reliability was drastically improved. By an introduction of this technology, 3-D structured MOS transistor having atomically flat gate insulator/Si interface can be fabricated.

Free Research Field

電気電子工学、電子・電気材料工学