2012 Fiscal Year Final Research Report
Integrated Circuit Design for Robust Operation under Low Supply Voltage
| Project/Area Number |
22300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
TSUCHIYA Akira 京都大学, 大学院・情報学研究科, 助教 (20432411)
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| Co-Investigator(Renkei-kenkyūsha) |
KOBAYASHI Kazutoshi 京都工芸繊維大学, 大学院・工芸科学研究科, 教授 (70252476)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 低消費電力化 / 低電圧動作 / 耐ばらつき設計 / ディペンダブル VLSI |
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| Research Abstract |
We have investigated on a design method that achieves robust circuit operation under low supply voltage of around 0.7 V. In particular, we have worked onthree topics:
(1) built-in self monitor and compensation of die-to-die variation
(2) sequential logic gates tolerating for within-die variation
(3) evaluation of dynamic performance variation under low supply voltage.
We have successfully developed variation-tolerant D-FFs, all-digital monitors and body-bias generator circuits for performance compensation, and accurate evaluation of delay fluctuation due to Random Telegraph Noise.
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