2012 Fiscal Year Final Research Report
Self-Aligned Embedded Metal Double-Gate Polycrystalline-Silicon Thin-Film Transistors Fabricated at Low Temperature on Glass Substrate
| Project/Area Number |
22560341
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku Gakuin University |
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Principal Investigator |
HARA Akito 東北学院大学, 工学部, 教授 (20417398)
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| Co-Investigator(Renkei-kenkyūsha) |
KITAHARA Kuninori 島根大学, 総合理工学部, 教授 (60304250)
SUZUKI Hitoshi 東北学院大学, 工学部, 准教授 (70351319)
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| Project Period (FY) |
2010 – 2012
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| Keywords | 電子デバイス・集積回路 / 薄膜トランジスタ / TFT / poly-Si / ダブルゲート |
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| Research Abstract |
Self-aligned planar metal double-gate n-channel (n-ch) and p-channel (p-ch) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) consisting of an embedded bottom metal gate, a top metal gate fabricated by a self-alignment process, and a lateral poly-Si film with a grain size greater than 2 μm were fabricated on a glass substrate at 550 ℃. The TFTs are called embedded metal double-gate (E-MeDG) low-temperature (LT) poly-Si TFTs. The nominal field-effect mobility and its subthreshold slope are, respectively, 530 cm2/Vs and 140 mV/dec for n-ch E-MeDG LT poly-Si TFTs, and 135 cm2/Vs and 150 mV/dec for p-ch TFTs. The superior performance of the E-MeDG LT poly-Si TFTs will contribute to the fabrication of high-speed, low-power CMOS poly-Si TFT circuits on glass substrates.
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